output the sbrio 9642 internal clock

[Yongxin]

In the NI sbRIO 9642 board, it has an original 40MHz internal clock signal. I want to use this clock signal to synchronize other components that is not the board.

I wrote a very simple vhdl netlist to do this job. Just invert the internal clock signal. But the output signal is constant, which is very strange.

Here is the vhdl code I am using

libraryieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

-------------------------------------------------------------------------

entity clockOut1 is

-------------------------------------------------------------------------

port(

      CLK : in std_logic;

      FOXB_CLK_OUT : out std_logic

      );

-------------------------------------------------------------------------

end clockOut1;

-------------------------------------------------------------------------

architecture clockOut_arch of clockOut1 is

-------------------------------------------------------------------------

begin

       FOXB_CLK_OUT <= not CLK;

end clockOut_arch;

While in the LabVuiew block diagram, it is like that.

Thanks,

Yongxin

[a_clucker]

Hi Yongxin,

Here is some information about using clocks with CLIP. There are also some examples of how to export the clock signal directly to a pin, which would remove the need for CLIP. Perhaps these documents can help you solve this issue.

How do you know that the output signal is constant?

Thanks,

Andrew

[David-A]

If the goal is to export the default 40MHz clock, you could try deriving an 80MHz clock from the 40MHz in the project, then placing a DIO terminal in  SCTL that uses the 80MHz as a timing source and toggle the DIO line every iteration. Edit: Not sure this will work on the 9642. The DIO lines haven't been validated at frequencies above 10MHz. 

Also, did you assign a clock to the CLK input from the CLIP Properties Page?

[Yongxin]

---

@a_clucker wrote:

Hi Yongxin,

Here is some information about using clocks with CLIP. There are also some examples of how to export the clock signal directly to a pin, which would remove the need for CLIP. Perhaps these documents can help you solve this issue.

How do you know that the output signal is constant?

Thanks,

Andrew

---

Hi Andrew,

I use the IP Node method to export the vhdl code, but will try your CLIP method later. The 1st example you give is instersting, I will try it later. 

I use the oscliscope to detect the output signal from the pin, it's constant .... 

Thank, 

[Yongxin]

---

@David-A wrote:

If the goal is to export the default 40MHz clock, you could try deriving an 80MHz clock from the 40MHz in the project, then placing a DIO terminal in  SCTL that uses the 80MHz as a timing source and toggle the DIO line every iteration. Edit: Not sure this will work on the 9642. The DIO lines haven't been validated at frequencies above 10MHz. 

Also, did you assign a clock to the CLK input from the CLIP Properties Page?

---

Hi David,

Sounds it doesn't work for that case that place a DIO terminal in the SCTL and output the clock signal directly. I will try your method anyway. 

I didn't use the CLIP method, so no CLIP property for me.

Thanks,