08-24-2009 03:56 PM
08-24-2009 04:41 PM
08-24-2009 04:52 PM
Edit: Forgot to include other problems with original code and why it wasn't working...
08-24-2009 05:13 PM
08-24-2009 05:31 PM
danilorj wrote:
It's a pretty nice attempt you did. But the way the vi is already done cannot be changed. I need to find a way of doing what you did but I have to maintain what it's done.
This is silly! There are so many things wrong with your VI. For example your 2D array will grow witout bounds if you run the VI consecutively.
Instead of the empty array diagram cnstant is all the FALSE cases, you need to wire the 2D array across the structure. try it!
08-25-2009 05:58 PM
08-25-2009 06:18 PM
You are building an array in a shift regsiter. Right?
Whenever a FALSE case is encoutered, you are placing an empty array into the shift register, thus deleting everything appended in earlier iterations. If you wire the 2D array across the FALSE case unchanged, nothing is added, but the existing contents of the shift regsiter is retained.
08-25-2009 07:32 PM
08-26-2009 03:12 PM
I just want some code that when the case condition is set to false then it clears the line from each channel. Only this.
I don't know if the use of formula node is a good option.
08-26-2009 03:40 PM
As already noted, if you insist on sticking with your design then just wire the data through in the False part instead of sending out an empty array. You also have to initialize the shift register and connect your graph to the shift register, and not create an additional tunnel, as shown in attached image.
I'd still like to know why you want to stay with your VI, which is far more complicated than what's already been presented as an alternative.