prevent FPGA recompile with new project reusing old FPGA code?

[jbeale1]

Whenever I create a new project with a new RT (real time) code, that reuses a previously existing FPGA-Main.vi and bitfile, Labview decides to recompile the FPGA code to a new bitfile. This is very time-consuming.  

Is this the correct behavior? If the FPGA code has not changed, just the Real-Time code changes, should I be able to reuse the existing FPGA bitfile?

[James.M]

I had this problem in the past, but I don't have the FPGA module anymore... so I know there's a way to initialize your FPGA reference using the bitfile instead of the VI, but I can't show you exactly how.

Right-click your init FPGA node and load from bitfile instead of linking to the VI and see if that does the trick.

[gregorelectric]

for documentation:

Can I Move My LabVIEW FPGA Project to a New Location without Recompiling? - National Instruments
http://digital.ni.com/public.nsf/allkb/B76C5ED987F464EC862579750059A761?OpenDocument