05-19-2014 05:02 PM
I currently have a collection of read and write functions on my FPGA VI that need to be running independent from each other. The issue that I am facing is that the read function writes to a DMA FIFO and every time that read function completes I want the FIFO to be read by the Host VI. I have tried putting these sets of VIs in a while loop to ensure independence, but when I do this the Host VI does not know when to read from the FIFO. I have tried adding interrupts when the read function ends, but this doesn't seem to be working either. I'm not really sure what else I can do to get the result that i am looking for. Any help is appreciated.
Thanks
05-19-2014 05:14 PM
Please post your code (ideally, both a screenshot and the actual VI), and describe the problem that's occuring in more details than "doesn't seem to be working." What actually happens when you run your code? How many DMA FIFOs are you using? What hardware are you using? When you say "read function" what are you reading from?
From your description, it sounds like you should assign a separate DMA FIFO to each independent loop, and then trigger reading the FIFOs on the host side using different interrupts.
05-20-2014 06:44 AM
I usually just always have my host reading the DMA in a loop on its own. I also add extra bits to the data in the DMA to tell the host what the data is. I use this to command the host when the acquisition is done and it can react however it needs to from there.