time violation with time loop

[abikutn]

Hi

We bought an NI 5761 with a NI 7951R FPGA module. In my design, I want to capture the data in 250MHz to an internal FIFO, and then do a multiply accumulation with certain codes stored in side the block memory. But I keep on having time violation error. Can anyone help with this? Thanks a lot!

[BillTür]

Which loop is giving you a timeout? Are all of your loops hooked up to a 250 MHz clock?
250 MHz doesn't leave you with a lot of time for your operations (4 ns) you will have to use a lot of pipelining to meet your requirements...

A few examples from what I can get in the code (assuming clock 0 is 250 MHz and clock 1 is less than that):
- one problem coming with using a FIFO in different time domains: it has some overhead (I'm not an expert in this)

- probably writing to FIFO takes some time, so isolate them via pipelines

- comparing two 32-bit integer might take some time as well, can you use another representation? if not, pipeline after that

You will have to check the timing information for the functions with highest latency and try and isolate them; the names of the functions (vhdl instance numbers) can be found in the description.

Hope this helps!

[abikutn]

Thank you very much for your reply!

One of the timing error comes from the comparitor, I will try to do a pipeline after that. 

Another timeing error is from the big single cycle time loop.

When I was doing this for channel (5 multiply accumulator), there was no problem for the whole program. However, when I change the big while loop to 2 channel (10 multiply accumulator), it gives problem. It seems because of the routing. When I scale it up, it delays 0.4- 0.2 ns. 

I will try your suggestions. 

Thank you

[Dave-C]

Hi Abhi,

I might also recommend checking out this KnowledgeBase article that explains functions that are and are not supported in the Single-Cycle Timed Loop, as well as other useful information about the structure.  Adding a second channel to the SCTL could certainly cause this problem, as it will return a timing violation at compile time if the loop cannot complete its functionality in a single clock cycle.  In this case, it would be best to split the channels into multiple SCTLs.

Regards,

Dave C
Applications Engineering