Vision Dev Module image processing FPGA

[mesolmaz]

Hello NI Community,

I am using 1473R board for real-time image processing. Specifically, I am building on the example (10-Tap 8-Bit Camera with DRAM (FPGA).vi). I would like to use Vision Module and its functionality (such as Low-Pass and Edge Detection) , but it seems that I can only process images when the pixel stream is 1 or 2 at a time. In this example, the data is sent to Host DMA is 64bit chunks. I was not able to sent the pixel stream in 8px because there is not an option for U64. 

Am I missing something here? I am able to create custom logic, as shown in the image attached. But I get wire mismatch when I want to synchronize with HOST DMA FIFO and use 64bit data.

[Kemens]

mesolmaz, have you tried using U8 FIFO with 8 elements being read at a time? Here are the FIFO settings I think that should get it to work out.

Host to Target DMA FIFO General PropertiesHost to Target DMA FIFO Data Type PropertiesHost to Target DMA FIFO Interfaces PropertiesIMAQ FPGA FIFO Pixel Bus VI

[mesolmaz]

Hi Clemens,

I believe I have to convert 64bit integer to Pixel Bus, but I am not sure if the other control signals included in the Pixel bus will sync. The 10px data is written to DRAM, packed to 8px before writing to FIFO. 

There is also the other 10tap 8bit example without DRAM. I was not able to make that one work with my Camera (Basler acA2000-340km). I only managed to work with 2 and 4tap settings. Also, the image processing library (filters, convolutions) does not seem to work on my FPGA card, NI 1473R-LX110.