80mhz reference clock to be routed to ctr output or pxi_trigger output

[kalyan1]

Hello Everybody,

If possible, I would like to route 6124 internal 80Mhz clock to any counter or RTSI outs. When I check daq card device routes on NI-MAX, I'm seeing that 80MhzTimeBase can be indirectly routed. However, I can manage to route it to Ctr1Source, for example, and I can't go any further. Please help me to get 80mhz clock as is from any outputs.

Thank you,

[Henrik_Volkers]

80 mHz wouldn't be a problem.. 🙂

but 80 MHz ...     I used these digital pins up to 40 MHz but run into problems at higher freqencies....(well, at these frequencies the cables, loads, driving circuitry, etc is important)

The spec isn't really clear about that, but most digital outputs seems to be specified up to 10 MHz.

What do you want to do with the 80 MHz ?

[kalyan1]

Hi Thanks for the quick reply..

Actually my plan is to source this clock to the spartan 3 fpga on my custom board. I'm trying to create 38.4 mhz clock internally in the fpga. I have 20mhz system clock on that board, and DCM in spartan 3 cannot support to generate it.

I actually generated daq ctr1 as 1.2 mhz, which is 38.4/32, the DCM allows me to use integer 32 at most for clock multipler .. even if specs says it can do it, in reality it didnt work out well. clock input of dcm cannot lock into for output, so couldn't generate. so instead of going up from 1.2 to 38.4, i wanted to go down from 80 to 38.4 that spartan 3 allows me to apply 12/25 fraction number for clock generation

Thanks, DANKE SCHON

[Henrik_Volkers]

You really should be serious with you shift key when it comes to units and metric prefixes.

For the rest,  propper use of the shift key eases reading!!

Have you tried a 1.2 MHz clock from a decent generator with a propper driver and cabling?  My guess would be that the DCM PLL can't lock because of signal degration... routing clock signals isn't just a wire! (At least on a PCB board, in LabVIEW it's a different thing 😄 )