04-05-2018 03:13 PM
Hello,
I need some help with a discrete control system I am developing. It involves generating a variable (not sine, square,nothing like that) analog output that must remain hold (Zero Order Hold - ZOH) for 20 ms (50 Hz) and such...... that I have constant sampling period with a computational load taking no more than 13 ms. That's it... nothing else. But I am having a bit of trouble, have a look.
Find a attached "Analog_Output_Test.vi" which sort of explains what is the problem.
In this VI, the lower graph plots the measured sampling time (period) using a diagram similar to those found in the example for generating Voltage Output (Non-regenerative). The problem with this is that it has WAY TOO MUCH JITTER (see photo).. I mean... seriously.. what is this even good for? I need something like the performance you get with a timed loop (see upper graph in photo), and this VI is not giving it to me.... I have tried other version wheres I put the code inside timed VI and stuff but eventually IT BREAKS... gives me error -200018 which is related to the frequency I am providing the data.
Can someone please help?
Regards,
Oscar
Solved! Go to Solution.
04-06-2018 10:36 AM
I sorted this out with this VI, just in case anyone has similar problem and wants to do something similar.
I just did a separated loop for generating the signal at very high frequency writting 1 sample so that it updates instantaneously. I couldn't start the code writting only 1 sample so I start with 100 and decrease to 1 as the program runs. I'm guessing there is some sync required there.
Regards,
Oscar