Proper TTL out through PFI line

[Oleks]

Hello everybody,

I am working on an application that recieves an analog continuous signal in the form of a sine wave (1kHz-5kHz) and needs to ouput a 5V TTL pulse (

TTL signal with positive logic 0 V to 5 V and a gate of  1 us) through one of the digital lines at each zero crossing.

I am using PXI 4472 and its analog edge capability do detect zero crossing and I am exporting "Start Trigger" signal to one the PFI lines available on my PXI 6221 board. I was under impression that the internal "Start Trigger" signal is of the kind that I need.

In order to test my program, I opened a test panel in MAX for my PXI 6221 card, selected the Counter I/O tab, and set the controls for Edge Counting and selected the output PFI6 line as the Edge Source. By Starting the Test Panel, and then running the LabVIEW program, I was able to record the rising edges of the Start Trigger being exported on PFI6. I tried various frequencies of the sine wave and, visually, everything was working fine. 

However, when I tried to read the signal through PFI6 line on the BNC2110 through an external osciloscope (Tektronix TDS 210) I do not see anything that would resemble a proper square-wave TTL signal, in addition to that, the camera that suppose to recive that TTL signal did not detect anything either. I can see that type of signal if I connect my scope to CTR0 and start Pulse Train in test panel in MAX. 

I was wandering if my approach is correct and maybe somebody can suggest what can be changed in order for my application to work.

Thank you in advance,

Oleks

[MaggieAggie]

Hello Oleks, 

Your approach appears correct. However, for your DAQmx Connect Terminals.vi, you are connecting the trig line in slot 2 with the PFI line on slot 3. Even though the trigger line will hold the same value at all modules, to connect the terminals you need to connect it with the the Trig line on slot 3 as well. 

[Oleks]

Hi Meggie,

Thank you for pointing that out. I probably saved my VI during the time I was "blindly" experimenting with diferent trigger lines in order to get anything from PFI line, that is why one of the lines was part of the device in slot 2 and another one from slot 3. The succesful edge counting was achieved when, everything was on the line of the device in slot 2(PXI 4472). However, neither my scope nor my digital aquisition system picked up a TTL 0-5V from PFI6. Would that be strange? Does the signal that I am exporting sutisfies the following conditions: TTL signal with positive logic 0 V to 5 V and a gate of  >1 us ?

Thank you in advance,

Oleks

[MaggieAggie]

Hey Oleks, 

Just to clarify, it was successful when "everything was on the line of the device in slot 2"? Are you still exporting your signal to the backplane and then to slot 3? 

The start trigger is a TTL signal. What do you mean by gate? 

If you have another PXI card, I would try to trigger that card off of the backplane so that we can verify that the signal was exported to the backplane properly. Then, we can determine why it is not being exported to the PFI line. 

[Oleks]

Hello Maggie,

By successful I meat I was able to count edges via MAX/PXI 6221/Test Panel. In that case, I exported Start Trgger to  PXI_Trig0 of PXI 4472(slot 2) and then connected PXI_Trig0 of PXI-4472(slot 2) to PFI6 line of the PXI-6221(slot 3). If by backplane you meant physical line on the hardware then yes, that is what I do.

Unfortunately we have only two PXI cards 4472 and 6221, so I can't really do the test that you suggested. Regarding the gate question, I think what the manufacture of the DAQ-Visualisation system meant was "high TTL gate input level(2 volts to 5 volts by common convention) with the pulse width equal or greater then 1 us". Unfortunatelly, my knowledge in Logic Gates is rather limited and this is just how I understand the manufacture specifications for the TTL external input.

Hopefully this will help,

Oleks

[MaggieAggie]

Hello Oleks, 

I want to re-clarify how you are using the Connect Terminals.vi. It is correct to route the trigger to the PXI Trig0 line in slot 2. PXI Trig 0 can be accessed from each module in the chassis. To export it to the PFI line in slot 3, access it from slot 3. 

I suggest making the change in the image below: