Specifics about analog output DNL value

[CDancer]

I have an application where I am using a PCI-6221 to generate a sine wave over a wide range of amplitudes (>1000:1). Obviously at lower amplitudes the waveform becomes quite blocky, but the harmonics that are generated by this are not a problem in this application, and I have found that using a small number of ADC steps has surprisingly little effect on the amplitude of the fundamental.

What is potentially more of a problem is the DNL specification of +/-1LSB. This means (I think) that if my waveform pk-pk amplitude is 65 DAC steps and it happens to straddle one of the glitches in the DAC's staircase its actual amplitude could actually be 64 or 66 steps.

My questions:

Is the DNL value stated in the spec sheet average or worst-case? Since the device has guaranteed monotonicity I think it has to be worst-case, in which case is there any data on what the distribution of DNL error is?

In the DAC in the 6221 does the largest step error usually happen at the point where the MSB changes state, which would usually be near the zero-crossing point?

If so, would it help to set the output range + and - values to asymmetrical voltages so my waveform is not sitting right on the MSB switching point?

Thanks in advance!

Chris

[John_P1 · Accepted solution]

Hi Chris,

You're correct that the worst case DNL is ±1 LSB (hence the guaranteed 16-bit montonicity mentioned in the specs page).  Here's a "typical" DNL distribution from the DAC manufacturer:

       

As for your second question, you may see glitching when the value of the DAC changes.  This glitch is not included in the DNL spec (which accounts for settling time).  You are correct that the largest glitch occurs when changing the MSB of the DAQ device (which is approximately 0V on the 6221, depending on calibration).  The glitch is accounted for in NI's specifications as "Glitch Energy" (see the specs page link above), and you'll probably notice the value is relatively high on the 622x.  The 625x and 628x have much lower glitch energy due to the use of a different DAC.

If I understand your third question correctly, the idea would be to adjust the range of the 622x so that the MSB change doesn't correspond to 0V?  Unfortunately, the 622x only has the single bi-polar ±10V range available, so you can't adjust the range to change where the MSB lies.  You could however output the waveform with a DC offset so that the MSB is never crossed, then use a filter to remove the DC component of your signal (assuming you want the sine wave centered around 0V).

Best Regards,

[CDancer]

Thanks John, That's really useful.

The typical DNL graph is very encouraging - nowhere near the +/-1 LSB maximum. Strange that the largest errors are bunched up at the high end, which is not what I would expect. I'd expect the top 50% to replicate the bottom 50%, because the only difference between them is the state of the MSB. Maybe it's not just a simple R/2R type DAC?

Knowing that about the output range is useful too. I'm sure MAX allows you to set the output range for the 6221 doesn't it? If so, does that have any effect, maybe just limiting the range of outputs without changing the resolution?