Usage of external reference clock input (refclk) and PLL with X-Series (PXIe6363)

[ni-switch]

I would like to use the PXIe 6363 DAQmx card to generate two analog signals.

To be in phase and to avoid drift with other external topics it is required to use the

external reference clock input at PFI<0..15> with a signal freq. of app. 15 kHz.

Belonging to X Series User Manual, chapter 9: Digital Routing and clock generation
Input of PLL: external reference clock: PFI<0..15> this should be possibel.

In classical PLLs designs the divider settings (pre-divider, post-divider and mainly the feedback-divider)

are know / programmable by the user for generating the requested output frequency.

Since the documentation is currently not clear to me:
1. Does this work with an input frequency of 15 kHz (specified input frequency range of PLL?)

2. What will be the output frequency of the PLL / programming of feedback devider settings of the PLL?

Thanks and best regards,

Andreas

[John_P1]

I think both your questions are answered in the 6363 specifications.

The input to the PLL must be either 10 MHz, 20 MHz, or 100 MHz depending on how you are routing the signal into the DAQ card (with PFI lines you could use either 10 or 20 MHz but not 100 MHz).

The output of the PLL is the 100 MHz timebase.

The 6363 can also take in an external AO Sample Clock or AO Sample Clock Timebase which would be more useful to you if you need to synchronize analog outputs with an external ~15 kHz clock.

Best Regards,

[ni-switch]

Thanks for giving the feedback with the possible PLL input frequencies described in the PXIe 6363 specification.

Using the AO Sample Clock Timebase or the AO Sample Clock would not work since I need a higher frequency for sampling out

an analog waveform at A0.

So currently it seems to me that I have to use the trigger -> retrigger option to synchronize the output signals with the 15 kHz input

signal.

Best regards,

Andreas Dierks