VB6 NiDAQmx gated counter m-series

[jdhNC]

I am using VB6 with an PCI-6013 card.

I am generating a gate signal on CTR0 (50Hz, 95% duty cycle) which seems to work fine.

I am counting edges continuously on CTR1. 

I want to count edges on CTR1 only while CTR0 output is high. When it drops low, I want to read the counts, zero the counter and wait for the next trigger. 

How do I trigger a read event based on the gate?

Do I have to manually stop/start the counter task to re-zero the counts?  I have done this in the past with traditional NIDAQ and don't recall manually retriggering.

Any suggestions or example code?

Thanks

John

[Kyle_A.]

Hi John,

For this application, what you should do is a CI Pulse Width task for CTR1, and specify your CTR0 signal to be the gate on CTR1.  The pulse width task can be configured to count ticks of the source and then store that information in the PC buffer on your computer. The measurement will reset itself since it is returning pulse width.  It will also return your pulse width at the falling edge of the gate, since that is when the pulse ends.

Try this out, I believe this should work as expected for what you are looking for.

[John_P1]

Hi John,

To further elaborate on what Kyle said, You can indeed implement this without manually resetting the counter task.  The key is to configure a Pulse Width Measurement which will reset the count register at the end of every period.  Using Implicit timing will ensure that you latch in a value at every falling edge of your input signal and will not miss samples.  It would look something like this (from the M Series User Manual--the E Series manual doesn't have the same diagram but the card should be capable):

The general code should be:

Create a CI Pulse Width Channel (DAQmxCreateCIPulseWidthChan).  Use DAQmx_Val_Ticks for the units parameter.  Start on the rising edge.

Set the gate to be the internal output of the other counter (DAQmxSetCIPulseWidthTerm).

Set the timebase to be the external signal you wish to count (DAQmxSetCICtrTimebaseSrc).

Configure "implicit timing" to create the input buffer and tell the device to latch data to it on every edge of the gate signal (DAQmxCfgImplicitTiming).

Best Regards,

[jdhNC]

Thank you for all the assistance.
I was trying to use SampClk instead of Implicit timing which seems to be unsupported.

JohnP - I am currently using pretty much what you detailed above.  Is this functionally equivalent to doing a 2 counter frequency channel and returning ticks?  This seems like it would sample on rise and fall which would eliminate my dead zone at the end of the gate.  Would a semi-period measurement instead of pulse width also do this?

The actual source to count is not available from here, so I'm simulating with a 1kHz signal from a scope.  That makes the numbers come out a little too perfectly for me to be confident that it works as desired.

Thank you again!

John

[John_P1]

It's true, Sample Clocked Period measurements aren't supported on E Series or on most M Series.  X Series (and 621x devices in a more limited and undocumented fashion) support them, but the behavior might not be exactly what you think it is--it's described in the X Series Manual if you're interested.  From your description it sounds like the behavior you are looking for is Implicit Timing anyway.

Functionally a semi-period measurement of an internally generated gate signal is pretty much equivalent to the 2 counter frequency measurement.  However you cannot set the 95% duty cycle that you were looking for if you configure the high frequency 2 counter method.  Anyway, the original problem description was:

I want to count edges on CTR1 only while CTR0 output is high. When it drops low, I want to read the counts, zero the counter and wait for the next trigger.

By "next trigger" I was assuming you meant the next rising edge of CTR0.  That's what the pulse width measurement will accomplish.  A semi-period measurement would count both high and low times and return a value on each edge of the gate signal (rising and falling).  So the resulting buffer will contain an array of [High Ticks, Low Ticks, High Ticks, Low Ticks, ...]

A 50 Hz 95% duty cycle is going to have a pulse width of 19 ms (±50 ppm)  Even if the scope is asynchronous to the gate signal, I'd still expect to see exactly 19 pulses--only if the source edge occurred at the exact same time as the gate would you get an different value--either a missed count at both ends (18), a counted signal at both ends (20), or one of each (19).  The window of opportunity for this to happen is very small (a few ns), especially relative to the 1 ms period of the signal.  For the vast majority of cases you should count 19 every time, 1 pulse during each ms of the gate signal:

If you generated a source frequency that didn't go evenly into the 20 ms period of your 50 Hz gate signal you should get variance in your results.  For example, a 625 Hz signal would have a period of 1.6 ms which goes into 20 ms 12.5 times.  If left running continuously you would expect to get alternating runs of 12 and 13 ticks, assuming the edge does not occur at the same time as the edge of the gate (where you could have consecutive runs of 12 or 13 ticks).

Best Regards,

[jdhNC]

Your answer to what I stated that I wanted was perfect!  I am modeling this system off one that does something similar and it was set up with 19mS high, 1mS low.  That timing seems to be a function of the scaler card that was used rather than a design requirement.  The counts will be more accurate with no deadtime, so I think the frequency measurement type will be more useful.

My last (I hope) issue is reading the counts. 

I wanted to use an EveryNSamplesEvent Handler but when I try to register the handler, it generates:

-200981 DAQmx Every N Samples Acquired into Buffer Event is not supported by the channel types or devices in your task"

Is there any way I can do that or another event I can trigger on without polling?

Thanks,

John