6581 spec is 200Mb/s for DDR - can module design handle 480Mb/s DDR for LVDS?

[dial]

The block diagrams show the DRAM interfacing to the FPGA via socketed CLIP nodes. The PXI bus is also shown going to the FPGA. Does this mean that any access from the Host VI to the RAM has to be via the FPGA?

I have tried creating some FPGA & HOST code after setting the target device as a FlexRIO and all seems to work out OK. However, I haven't yet found anything that allows the host VI to do read or writes to the DRAM. It's not showing up in the drop-down list for Invoke Method. I've enabled the DRAM on the project resources but haven't yet built an FPGA bitfile that uses it so might this be the reason it's not showing up?

We're looking at using the FPGA to so some image processing so would hold the image data in the DRAM. That means we're going to be looking at transferring large blocks of data via the PXI to/from the DRAM so the transfer mechanism and rates for small and large images is of particular interest. We wouldn't be sharing the PXI bus with other boards and so hopefully the data rates will be close to the bus bandwidth.

Regards

Dial

[BrowningG]

Hello Dial,

You are correct, in order to transfer data from your host PC to the DRAM, the data will first have to pass through the LabVIEW Block Diagram.  With socketed CLIP, the block diagram is given access to a set of CLIP I/O that becomes the LabVIEW interface.  The CLIP also has access to a set of socketed I/O that is fixed depending on what socket you are using.  For instance, the adapter module has one set of socketed I/O that is defined by the hardware interface (things like GPIO, clock lines, etc.).  The DRAM has a set of I/O that is fixed by the interface required for hardware memory access. 

The host VI does not have access to the socketed I/O without first going through the LabVIEW FPGA Block Diagram.  In order to transfer data to your DRAM from the host PC (such as an image), you would probably need to use a DMA FIFO to ensure no data is lost during the transfer.  The host PC will push data into the FIFO, while the FPGA block diagram will pop this data from the FIFO and push it to the DRAM interface.  The DRAM is theoretically capable of 800 MB/s based on the 200 MHz DDR interface used by the CLIP, so it will be your PXI bus bandwidth that will be the bottleneck of your data transfer.  In theory that would make your data rate approach that of PXI bus bandwidth if your streaming architecture allows for it.  

Check out the examples, Memory Integrity Test.lvproj and Memory Throughput Test.lvproj some ideas on how to use DRAM on your FPGA block diagram.  The example NI 6581 Continuous Waveform Generation - Advanced.lvproj for the NI 6581 shows how to send two waveforms to the FPGA target via DMA FIFO to be stored into the target's DRAM.  The waveforms can then be controlled by the user to be generated through the two connectors of the NI 6581 Adapter Module.  This seems like it is similar to your idea, so this example might give you a good idea of how to stream data from the host into the DRAM and then do something with it on your FPGA.  Hope this helps!

Regards,

BrowningG

[dial]

Thanks. Both explanation and pointers to examples (not sure how I'd missed them) are most helpful.

I'll need to wait for the hardware to check them out but the examples will allow me to prepare.

Dial