Any experience of using on-board DRAM in FlexRio board?

[hjkee]

Hi,

I am implementing LV FPGA module. I'm wondering if there is a way to use on-board DRAM as the external memory of

my FPGA design. In a block diagram of FlexRio, it is possible to trasfer data between FPGA and DRAM thorugh a CLIP node.

I am not sure how to make it work. Please share your experience for these.

Thanks,

[BrowningG]

Hello hjkee,

To get started with the FlexRIO DRAM, I suggest looking in a few places.  First, the LabVIEW help has an entire FlexRIO section dedicated to DRAM.  This can be found in the help path: FPGA Module >> NI FlexRIO Reference and Procedures >> Configuring the Onboard DRAM Interface.  In this help book you will find information about the individual DRAM signals and other great getting started information.  Reading through this whole book will help you program with DRAM efficiently so you can avoid unnecessary compiles.  Also, there are several shipping examples that show the various ways to use the DRAM CLIPs.  From the NI Example Finder (Click Help >> Find Examples from the LabVIEW environment) navigate to Hardware Input and Output >> FlexRIO >> External Memory. 

There is one FIFO CLIP example and two random access CLIP examples.  The Memory Integrity Test example gives a good introduction to how to use the random access signals while the Memory Throughput Test example shows one method to get close to the theoretical 800 MB/s throughput that is possible with the DRAM used on the FlexRIO FPGA module.  I suggest starting with the integrity test to learn how the CLIP signals are used and then move into the throughput test for ideas on how to optimize your code.  Let me know if this helps!

Regards,

BrowningG

[hjkee]

Thanks for letting me know good information about help pages.

In my LV86, I can't find out any help page related to FlexRio.

(I've installed device driver Aug2008 version)

How can I install the stuff related to FlexRio?

[BrowningG]

Hello hjkee,

To program a FlexRIO, you will need LabVIEW 8.6 (or newer), LabVIEW FPGA 8.6 (or newer), and NI-RIO 3.0.1 (or newer).  You can find a copy of NI-RIO on the drivers and updates page.  NI-RIO 3.0.1 released after the August 2008 driver CD was released. 

Regards,
BrowningG

[hjkee]

The help page and examples is very useful to understand how it works.

I got questions in 'Random Access - 64 Bit Memory Interface'

What is the maximum bandwidth we can achieve?

FIFO - 64 Bit Memory Interface seems to simultaneously read and write data at speeds up to 40 MHz.

Does Random Access - 64 Bit Memory Interface show a simliar performance?

What does 'Random' mean in the name?

[BrowningG]

Hello hjkee,

While on the surface your question bandwidth question is fairly straightforward, it can get complicated.  First, the random in the random access CLIP means that the DRAM will behave like random access memory; this CLIP you can send read and write commands that will access the DRAM by address.  You can use this CLIP to maximize the bandwidth of the memory access. 

The random access CLIP has the ability to access the physical memory at 200 MHz DDR across a 16 bit port.  If every clock cycle of the random access CLIP is used for memory access, then we can push data into or pull data out of the physical memory at 800 MB/s (200 MHz DDR * 16 bits).  The DRAM CLIPs provide a 64 bit interface to the memory for LabVIEW.  As a result, a 100 MHz clock is provided as a base clock on the FlexRIO to prevent your block diagram from artificially limiting your bandwidth (100 MHz * 64 bit = 800 MB/s).  The memory throughput example accesses the DRAM CLIP using this 100 MHz base clock. 

DRAM is by nature volatile.  As a result, the DRAM CLIPs need to ensure that data stored in the physical memory remains valid.  This means not every clock cycle of the DRAM CLIP can be used to transfer data to and from the physical memory.  To increase the efficiency of the CLIP, I recommend that you attempt to access the DRAM by sequential addresses and to perform multiple reads or writes in a row.  An access pattern that reads 4 times in a row and then writes 4 times in a row is going to be more efficient than an access pattern that alternates the reads and writes (for example: RWRWRWRW). 

I suggest that you carefully review the Memory Throughput Example to see one idea of how to maximize efficiency.  By changing the number of sequential reads that are performed, the write and read bandwidth will change.  You should also note that the total throughput will not add up to 800 MB/s because the random access CLIP has to ensure that the data stored in the DRAM remains valid, this will consume some of the CLIPs clock cycles.  Use this example to get an idea of the throughput under different conditions. 

Regards,
BrowningG

[nanocyte]

I flipped through the examples and they all seem to use "LabVIEW FPGA Memories" for their DRAM Properties. I'm guessing there was an interface update at some point that made the interface more flexible. Is that right? Are there any socketed clip examples? I don't necessarily need them but I'm a little curious.

[Terry_ALE]

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@nanocyte wrote:

I flipped through the examples and they all seem to use "LabVIEW FPGA Memories" for their DRAM Properties. I'm guessing there was an interface update at some point that made the interface more flexible. Is that right? Are there any socketed clip examples? I don't necessarily need them but I'm a little curious.

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Socketed CLIP interfacing to DRAM is not used any more.  I do not know when it stopped being a thing.

See the following shipping examples for using DRAM:

1. PXIe-791X Getting Started.lvproj 

2. Getting Started - External Memory.lvproj 

3. Memory Throughput Test.lvproj 

4. Memory Integrity Test.lvproj

5. ATCA 3671 - Getting Started DRAM.lvproj

Generally, the DRAM IDLs for random access or FIFO access are the two ways they are used.