FIFO DRAM

[James Hall]

Hi All

I was just wondering, if I use the FPGA Invoke method "reset" will this clear the DRAM if it is set in FIFO Mode?

I understand the DRAM is volatile so I would guess it does lose the data, but while looking through the LabVIEW website I found this

http://zone.ni.com/reference/en-XX/help/371599E-01/lvfpgahost/fpga_method_reset/

It says in there "This method does not reset memory." which has confused me a little.

Any help would be great

[BrowningG]

Hi James,

Both of the DRAM interfaces use Component Level IP (CLIP) to provide an interface between the LabVIEW FPGA diagram and the DRAM chips on the FlexRIO.  All CLIPs have the ability to use a single asynchronous reset so the VHDL code in the CLIP can be reset when the VI is reset.  You can see more details on VHDL for CLIPs here.  Whenever the reset method is called from your LabVIEW FPGA host VI, the asynchronous reset signal in the DRAM CLIP is asserted.  This forces the DRAM interface to reset, which will cause the DRAM (both the FIFO and Random Access) interface to be cleared.  The link you mentioned is referring to FPGA Block RAM memory components.

Also, the DRAM is volatile so a system shutdown will also clear the memory.

Regards,

Browning G

[BrowningG]

Hi Again James,

When you call the Reset Invoke Node, the DRAM is forced to reinitialize.  This reinitialization involves multiple precharges and refreshes of the DRAM and will not cause all of the data in the DRAM to return to a value of 0x0.  Instead the data in the DRAM will appear more random if you try to read any of the addresses in the random access interface without first writing to them after a reset.  However, calling the Reset method will cause the DRAM FIFO interface to appear empty since the input and output block RAM FIFOs used in the CLIP will be reset. Let me know if you have any questions.

Regards,

Browning G