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修改时间 01-07-2019 02:52 AM
对PXIe-5172 FPGA编程中,我对CH0采集到的数据做了一定处理,举个例子吧:每40个数据(通过模板进行匹配)视为1个数据通过FIFO(0)传递至PC端,所以在采集开始的时候可能不是40个完整的数据所以被舍弃了。CH1的数据不做任何处理通过FIFO(1)传递至PC端。出现的问题就是CH0和CHI的数据没办法对齐,所以没办法检测相位(两通道最终都是正弦信号)。两个FIFO都在单周期定是循环里运行,125MHz。
我应该如何处理使两通道信号对齐呢?
已解决! 转到解答。
修改时间 01-07-2019 11:19 PM
您好,
这个论坛可能对您有帮助:https://forums.ni.com/t5/LabVIEW/Synchronizing-DMA-FIFO-Buffers/td-p/2980695
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