LabVIEW FPGA RF Communication Library 2.1.0 - PLL - Example

[Vincent_R.]

Hi,

I'd like to use the PLL function offered by RF FPGA Toolkit I downloaded on NI-Labs. I haven't found any example related to this feature.

Before compiling anything, I designed a small example to simulate under LV Windows.

In the example joined, I defined that I expect to have a theorical frequency value of 60Hz but I have an actual value of 59.5Hz.

I'm not sure if I use correctly the function. Can somebody confirm?

For the alpha parameter, I don't know neither what value to set.

NOTE: even if I set an actual frequency of 60Hz, it doesn't seem to work or maybe I don't simulate during a sufficient long period.

Best regards.

Vincent

[hongpku]

Hi Vincent:

The main reason the PLL can not get locked is that the alpha parameter is too large. In PLL, there is a loop filter,

It is used to suppress the high frequency in the output of the phase detector, so it should be a low pass filter. To make it a low pass filter, the value of parameter alpha should not be too large. The attachment is the modified vi, i modifed the value of alpha and the total number of samples.

BTW, it needs quite a while to run:)

[richtian]

Hi, Vincent,

I have several things to add.

1. Go to the control context help for more information on each control/indicator of niFPGARFv2 PLL.vi.

2. I'd recommend you start with alpha = 0.001 and tune it smaller and smaller. You can observe the f about the convergence procedure and the accuracy in stable status. The smaller the alpha is, the longer it takes to be stable and the more accurate the f is. However, since it's fixed-point math, if you make the alpha too small, the fixed-point math will be unhappy to work well. In your example, I think alpha = 0.00025 is ok.

3. To simulate the PLL on desktop is really slow. Because it's a point-by-point computation. I'd recommend that you write a simple FPGA VI to do processing using niFPGARFv2 PLL.vi on FPGA, and feed/get data to/from FPGA. That's much much more efficient. Cheers for power of FPGA. I'm attaching my example FYI.

Thanks,

Tianming

[erik09]

Hi,

I know it is a long long time ago, but I would like to come back to this topic. I tried the codes you posted here and executed them on my FPGA. For the frequency everything looks great. It locks, when I set the parameters appropriate.

I have a problem with the phase. When I readout the phase, I expect to see a flat phase after a while. But no matter how long I let the loop run, the phase increases further and further. I want to generate a signal sin(2f*t+pi*z) from frequency and phase, but this does not give a good result.

Does anyone see what I do wrong when acquiring the phase from the PLL?

Best, Erik