NI FlexRIO Development Tools Discussion

[o.fujioka]

Hello Dlinniy,

I am a FIDL freak and started without any manual.  All what I did to learn FIDL were start from example and check the behaviors of each FIDL APIs by executing FPGA VI on development computer.

Since we can make FPGA timing chart by "sampling probe" on LabVIEW 2013, it might be easier to learn FIDL than before LabVIEW 2012.

All you have to remember is set the installing directory to ...\National Instruments\LabVIEW 2013 when you install FIDL 1.1.

(There is a method to acheive timing chart in simulation before LabVIEW 2012)

As dklipec says above, there are multiple examples for getting started.

In my opinion, there are two levels in difficulty for the FIDL example projects. 

Easy level example shows how to utilize some VIs in FIDL >> Acquisition Engine palette.

C:\Program Files (x86)\National Instruments\LabVIEW 2012\examples\FlexRIO\FlexRIO Building Blocks\573X\Simple

Difficult level example shows how to utilize some VIs in FIDL >> Flexible Record Storage and FIDL >> Memory

C:\Program Files (x86)\National Instruments\LabVIEW 2012\examples\FlexRIO\FlexRIO Building Blocks\573X\Acquisition Engine

To be honest, I have not pushed myself to master all the APIs on FIDL.

Actually, I completely understood all the APIs on FIDL except for Flexible Record Storage APIs.  (I would like to have help for these APIs, too)

My recommendation is try to run the Simple Acquisition Engine example (easy one above) by FPGA simulation, first.

With that, you would see how each APIs in Acquisition Engine palette work.

After that, since data bandwidth to host computer is very large with FlexRIO, you may want to store data on DRAM once.

Then, transfer data from DRAM to host computer like fetch back log with NI-SCOPE.

In that situation of DRAM handling, you can also simulate DRAM by executing FPGA on development computer.

Then, you will see how easy to implement DRAM storage with FIDL >> memory palette.

[tstahl]

Is there a version that will install with LabVIEW 2012? The installer for the 1.3 version notifies that I "must install LabVIEW 2013 32-bit on the system before you can run this setup."

[dklipec]

The 1.1 version can be installed into LabVIEW 2012.  As a "Labs" release, it isn't viable for us to maintain compatibility for all previous versions of LabVIEW, particularly as we take advantage of new LabVIEW FPGA features.  The 1.3 release specifically relies on "new in 2013" features to function, and therefore cannot operate with an older version of LabVIEW.

However, the 1.1 version is now attached to the main download page so that users who need to install to older LabVIEW versions can continue to download and use the previous version.

[RikPrins]

I get the same message: "must install LabVIEW 2013 32-bit on the system before you can run this setup.". However I have install LV 2013 (SP1) 32 bit. But I also have LV 2014 installed, is this causing a problem? How can I get past this?

[pi-2D2]

Same thing happened to me after I installed LV2014.

[j.artis]

Hi,

I'm having trouble getting any of the example code to work.

Can you post a minimal code project for PXIe - 7966R + NI 5762 (-02) on the FlexRIO.

Thanks,

John

[Valentin87]

Please tell me, can i use Tools with NI 6585 or NI 6587?

[dklipec]

There are not examples for how to use it, but you could just replace the analog I/O nodes from one of the examples with integer I/O or bits packed into integers with a digital adapter module.  Clock configuration is a separate concern for digital modules.

If you are looking for some of the "basic elements" or memory wrappers, many of these ship with the product now under instr.lib/_niInstr.  If there are specific blocks or examples that you would want to see ported from this tool distribution into the shipping version, I'd appreciate hearing that feedback.

[Valentin87]

I guess that this loop is config clock FPGA.

I would like to know how correctly create this loop for NI 6585? Is it possible?

[dklipec]

I hate to answer with a "that depends," but... that depends on how you are clocking your logic.  In the digital adapter modules for FlexRIO, there isn't a clocking chip on the adapter.  You use the clock in the diagram by creating a clock of the appropriate speed in the project and running your single cycle timed loop on that clock.  You can also bring a clock in on a clock capable pin (see the documentation for the digital adapter modules).  For static configuration of clocks, this is all that is required, and using the clock config VI isn't necessary.

In principle, you should be able to create logic in the CLIP and your own clock config VI to actually mock this interface to allow you to switch clocks at run time.  If you have loops that need to be reconfigured at run time, this would be a reasonable starting place, but you will have to do VHDL work in a custom CLIP to make that happen.