what's the smallest time step of NI Linux RT simulation on HIL application

[Bigbigbang~~~]

Hi

     I have a application which use Simulink model deploy to NI Lnux RT system by NI Veristand,do you know what's the smallest time step of NI Linux RT simulation on HIL application?

     I know there should have difference on different level of simulation model scale, except that, which factor will made impact on the time step? PCL loop or other？

     and with the same simulation model, to improve the time step,is there has different between different configuration on veristand? so you have recommend configuration? 

[jalfonso]

The minimun step depends on the CPU power . My old two core 10 years old pharlap Desktop PC  system sucessfuly runs 1KHz Simulink models , connected to CAN, EtherCAT and Ethernet/UDP nets.  I tried smaller step times (400 micro secs)  and runs OK.

In specific cases where a section of the model must run faster, I run a simulink model 5 times in a step of the PLC, but in this case, the inputs are constant during the 5 cycles.

The PLC defines the steptime used in the simulation. You can use decimation in each model for save cpu time and runs many times the models with smaller characteristic times. 

In case you have several models, you can define the order of resolution of the models and how inputs of the models refresh. This could impact in the stability of the simulation. Also the solver (Euler, Runge Kuta..) could impact the stability.

My PC only have two cores, so running the models in parallel is not feassible, and I got best results using Jacoby resolution (model by model).