Engine Simulation Custom Device Feedback

[Devin_K]

Hi Vijay,

Did you install everything listed in the Software Requirements section?  The VIs and templates you're missing should be included with the Automotive Engine Simulation (AES) Library for HIL.

[Vijay Chand]

Devin and Marc

Thanks for your suggestions. I could eliminate the error, by installing the AES library 2010!! Previously i have installed the 2009 folders.

Will get back if i face some other problems! Kudos for the efforts in making the library!

[Vijay Chand]

Devin and Marc

I tried compiling the FPGA code for the custom device, however I am recieving a timming error. I tried reducing the time complexity by replacing U64 variables to I8, however it is not affecting it enough to run in 25ns loops (This is for the Crank signal generation loop).

Please suggest a solution for the same. I have attached a screen shot of the error along with the time analysis.

Thanks,

Vijay

[StephenB]

That is surprising. Can you post the project (zipp'd) and tell us what physical target you are using?

Important note: you cannot change the data type of the required controls or indicators. If you do so... they will not be recognized by the custom device when you select your bitfile.

One idea: try changing your FPGA compilation options to optimize timing performance. This is in the build specifications menu.

[Vijay Chand]

Stephen,

Thanks for your reply.

I have tried changing the compilation options to optimized timing, but the error still pops up.

I am attaching the zipped file of our project. Following is the hardware and software description of my setup.

Hardware:  NI_PXI 1042 chassis, 8186 RT embedded controller, 7831R RIO FPGA device.

Software: Labview-2011, Veristand-2011, Veristand FPGA wizard-2011,NI-FPGA2011, Xilinx Compiler 10.1, Engine Simulation Custom device 2011,AES 2010+,Matlab Simulink 2008b.

Thanks,

Vijay

[Devin_K]

Hi Vijay,

The reason for the error is that you are using older hardware (7831R) which does not have as fast of an FPGA as our newer models.  This custom device was designed to work with 784X and 785X cards, but not necessarily with 783X.

If you don't want to upgrade your hardware, you can make it work with the 7831R, but you will need to make some modifications.  The problem is wit hthe timing in the "N Teeth M Missing Generation Loop".  To fix it, you could either pipeline the logic in the loop (add shift registers between elements in the critical timing path), or more some of the logic outside of a single-cycle timed loop.  For more information, check out the second post here:

https://decibel.ni.com/content/thread/9068

[Devin_K]

I just realized that the link I posted above is to a private community group that you may not have access too. I have attached an example of how you could modify your code to get it to compile using pipelining between the multiply and the generation calculation

Note:  Since all of the controls are set asynchronously from the host, and the global reset is used to initialize the generation subVI, it is not necessary to add any additional feedback nodes.

[StephenB]

I would recommend taking the multiply and add out of the single cycle timed loop. These are only used to calculate the settings for the generation... and the settings usually don't change after RT initialization. So you can just move them into a parallel while loop.

Your compile should be a lot easier this way.

[Vijay Chand]

Thanks Devin for your useful information.

Stephen, your suggestion worked! I've placed the math blocks in a while loop and it got compiled. Thanks a lot!

Can you eloborate on "Modify XML to define the I/O going through the NI VeriStand itnerface" in  step no 5. I also suggest that you add the same explanation the main page so that it'ld help anyone using it.

Thanks

Vijay.

[Devin_K]

Hi Vijay,

In step 2, you create an FPGA template with the NI VeriStand FPGA-Based I/O Interface Tools.  These tools are used to create an FPGA personality that can be integrated in NI VeriStand under Hardware >> Chassis >> FPGA.  This process involves having an FPGA template VI, modifying it to meet your IO needs, and then defining the corresponding XML so that NI VeriStand knows how your packets are defined.  The "NI VeriStand RIO Library" section of the above linked document describes how to do this.

Many users who are using the Engine Simulation Custom Device will also want to make use of the native NI VeriStand FPGA support for the rest of their IO, so they would need to follow all of the steps.  In your case however, I assume you don't care about other IO (the top loop in the VI you attached was empty, so Stephen and I both deleted it in the examples we posted).  In that case, you don't need to worry about an XML file.  All you have to do is compile your VI into a .lvbitx, add the custom device to your system definition, then select the "User Specified FPGA" option and browse to your bitfile.

I agree that the instrctions could be updated to add some more clarity.  I plan on doing that as well as probably adding a project with a couple example FPGA VIs.

Regards,

Devin