Engine Simulation Custom Device Feedback

[Vijay Chand]

Thanks Devin.

Our loop was empty becuase, I have started with only a crank signal first. I want to prove the usage of Veristand to people around here. After that, I woudl anyways procced for the entire engine model.

The problem here is I have used PXI for data acquisition earlier, and hence all this procedure a bit deviating from the traditional way I use NI- hardware-software combo.

Will try  the method suggested by you.

Kudos for you and Stephen for your  timely and resourceful responses.

Will post back with any scussess or further queries.

Vijay.

[Vijay Chand]

Dear Devin,

I am facing problem in building and adding the custom device. I have compiled the .lvbitx file as advised. However, the custom device created finally using the NI Veristand FPGA Wizard contains different types of files as compared to the default examples.

I have added the created project folder into the custom device folder in C:\Documents and Settings\All Users\Documents\National Instruments\NI VeriStand 2011\Custom Devices\

However, now the custom device does not appear when I right click in custom device icon in system explorer in Veristand. Is this the right way to add the custom device?

If I do not have to create the xml file, is my custom device completed? or do I have to follow some more procedure to build the custom device.

I have added a screen shot of the files generated by steps mentioned. Please tell me if I am going wrong somewhere or I have to follow any further procedure.

Thanks and Regards,

Vijay

[Devin_K]

Vijay,

The FPGA project and bitfile are not the actual custom device, they are just used by the custom device.  These files should not be located in the "Custom Devices" folder.

Download the .zip file attached at the bottom of the custom device page and follow the instructions in the "readme.txt" to install the custom device.  You will then be able to add the custom device to the System Explorer by right-clicking "Custom Devices" and selecting National Instruments >> Engine Simulation.  When you add the custom device, you will be prompted for your bitfile.  You can either specify the path to the .lvbitx file you created, or if yoiu have already added your bitfile to the Chassis >> Hardware >> FPGA section, you should be able to select it from a list.

[Vijay Chand]

Dear Devin,

I am not being able to add the bit file in this GUI prompt. It says invalid bit file.

I have compiled the bit file using Xilinx 10.1 tools. And it’s made for 7831R.

(Could any of this be one of the reasons?)

Another reason I thought it could be is, I haven’t built the code for the entire library (only for Crank Signal is built)

Also I am not able to choose the first option (NI Veristand FPGA)

Could you suggest me what could be the issue?

Thanks,

Vijay

[Vijay Chand]

Hi Devin,

Could you please post the lvfpga project also for reference. The one you are using to build the bit file.

I am not certain about what should I do in the communication loops.

Thanks,

Vijay

[Vijay Chand]

Dear Devin,

I tried to build the bit file for the entire custom device also. And I am getting an error stating invalid data types connected to subVI, during compilation. I have checked all data type connections that I made, and they seem to be alright.

I am attaching my Labview project as a zip file. And also the error snapshot.

Also could you tell me whether, the bit file once generated, is to be directly called. As mentioned above we could not add the bit file generated to the project, when we built it only for the crank signal.

Can you please once try adding the bit file in custom device project?

Thanks and Regards,

Akshay Goel

(from Vijay’s Team)

[StephenB]

Akshay,

Your project has a single VI under the FPGA target named "Custom Personality FPGA.vi" which is located inside the "LabVIEW FPGA Engine 2" directory. That directory is not included with your zip file, so the file is marked as missing. Your zip file does include a "Custom Personality FPGA.vi", but this VI is inside the "LabVIEW FPGA Engine" directory... so I don't know if this is the right file for me to be looking at considering your project does not reference this file.

[StephenB]

We will soon be improving our documentation and code with a few changes:

1. We will clarify that you do not need to use the NI VeriStand FPGA Project Wizard. You only need to do this if you want to have additional I/O in the FPGA bitfile made available to NI VeriStand (for example: analog, PWMs, etc).
2. We will attach an example project to the add-on post so people have something to reference.
3. Currently the user must create a Host to Target DMA FIFO in their project because of the FullyCustomTeeth loop, or else their FPGA VI is broken. We will fix this.
   Details on the changes, if you care:
   • Remove the requirement for a Host to Target DMA FIFO from the template (and update the custom device to not use the DMA FIFO unless it is found).
   • Replace the DMA FIFO logic with a point-by-point register load from the host into a locally scoped FIFO
   • Place the locally scoped FIFO as VI-defined into the template... so the user won't have to configure this in the project and the VI isn't broken by default.

For right now, I have attached a zip file you can use for an example. This has two folders in it:

1. No NI VeriStand - Project and bitfile that has nothing else in it but engine simulation
2. With NI VeriStand Template - Project and bitfile that has a bunch of other example IO inside of it, using the NI VeriStand FPGA-Based I/O Interface Tools.

Have a look at the projects and see the difference.

If you only need engine simulation and nothing else... use #1 by adding the custom device to the system definition file and selecting the bitfile directly.

If you need engine simulation and need other things in that bitfile as well... use #2 by adding the bitfile to the system definition

[Vijay Chand]

Hi Stephen,

Thanks for sharing the project. We were able to run it at our end.(using method#1 above, where we are using the exisiting FPGA code). However, I would like to now add additional digital and analog I/O's to the project( of the same FPGA card).

I understand that I've to use the method#2 described by you,however it would be helpful if you could share details about how to modify the XML file. Is there anything additional to building the new FPGA bitfile and XML file to realize this functionality.

Thanks again for your help.

Regards,

Vijay & Akshay.

[Devin_K]

Hi Vijay,

Adding additional IO to your FPGA bitfile will involve using the NI VeriStand RIO Library posted here: NI VeriStand FPGA-Based I/O Interface Tools.  Read through the "Framework Template" and "NI VeriStand RIO Library" sections of that document to understand how to use the tools to develop your FPGA personality.  For most IO (built-in R Series IO and C-Series modules) you just need to drop down a VI from the API and wire up your IO.  For the XML, just open up the VI you dropped, look at the block diagram, and copy-past the comments into your xml (.fpgaconfig) file at the appropriate place (make sure the order of your packets in the XML matches the order of the packets in your VI).  For more information on the tags used in the XML, also take a look at this help document:  Creating a Custom FPGA Configuration File.

Note that this FPGA customization is not directly related to the Engine Simulation custom device, so if you have additional questions, you're better off posting them on the NI VeriStand Discussion Forums.

Regards,

Devin