Engine Simulation Custom Device Feedback

[ToddK]

Stephen & Devin

The Angle Processing Unit Loop in my FPGA code is not reading in the APU.Degrees per Tick value, causing my Crank and CAM generators not to output valid digital pulses.  How does the Engine Simulation custom device pass the Engine Speed value into the FPGA code?

VeriStand 2010, AES Library V2.4 - 2010, VS Add-On Engine Simulation Custom Device VS2010 V1.2, NI VS FPGA based I/O tools for VS2010 V1.1.2, NI-RIO 4.1.

Regards,

Todd K.

[StephenB]

Can you post your bitfile here so I can take a look at it? Just the compiled bit file should be fine for now.

What hardware target are you using?

The custom device just writes to that control by name.

[StephenB]

Oh and how are you confirming that the control is not being written to?

One technique I use is to hit run on the VI from labVIEW while NIVS is running... the LabVIEW VI will connect to the running hardware and you can see the front panel. really nice for debugging

[ToddK]

Hardware is a PXI-7842R and NI-9474-DIO modules in a 9151 expansion chassis with a PXI-8110 RT controller. 

For debugging purposes, I’m using the DMA read channels to return the Degrees per tic and Crank Angle values as FPGA channels and viewing from a workspace control.

The fpgaconfig and bitx files are attached.

Additional Source code was provided under support reference #7351736

[StephenB]

Todd,

I don't see anything wrong with the bitfile or the custom device that would prevent this FPGA control from being written by the custom device.

I did notice that the way you're reading the control back into the DMA is wrong, causing your debugging to be invalid. You have the APU Degrees per tic and APU crank angle packets defined in the XML as U64s with a sacle of 1. This is not valid and will cause the value to be rescaled in a way you're not expecting. See the scaling information provided at the bottom of this help document: http://zone.ni.com/reference/en-XX/help/372846C-01/veristandmerge/creating_custom_fpga_configuration...

Noteably, the scale value defines what full scale range the number should occupy. So a scale of 1 means the numbers full scale is compressed into the -1 to 1 range.

Also, you should be using FXP instead of U64 because the actual FXP representation of that number is Signed, 47, -4. In the end, it should look like this:

	<FXPI64>
	<Name>APU Degrees per Tick</Name>
	<Description>AES Engine Simulation RPM Calculation input to FPGA *Default Value +99</Description>
	<Category>Input\Analog</Category>
	<Unit>Degrees</Unit>
	<Symbol>AI</Symbol>
	<FXPWL>47</FXPWL>
	<FXPIWL>-4</FXPIWL>
	</FXPI64>

That will give you the actual FXP value back.

However, all of this to say... this is a much more difficult method of debugging than I would recommend. Instead, run the NIVS project as is... then open up your source LabVIEW project (the one that you made the FPGA bitfile with)... veryify the IP address is correct on the PXI RT Target and the RIO Resource name is filled in on the R series card (should be RIO0 or RIO1... etc... on the properties of this item)... then just open up your FPGA VI and click run. It will connect to the running FPGA and allow you to see its front panel.

[ToddK]

I found that if I change the FPGA Configuration file within my existing system definition, the Engine Simulation custom device will not re-link to reflect this change.  I must delete the Engine Simulation and FPGA, then add the new FPGA, then add the Engine Simulation custom device, then reconfigure the System Mappings.  

Is this an issue with VS2010 or a known standard procedure required when updating and existing system defintion with new fpgaconfig files?

VeriStand 2010, AES Library V2.4 - 2010, VS Add-On Engine Simulation Custom Device VS2010 V1.2, NI VS FPGA based I/O tools for VS2010 V1.1.2, NI-RIO 4.1.

Thank you for your help.
Todd Kutzner – Digalog Systems Inc.

[StephenB]

Hmm. That shouldn't be neccesary unless you change the path to the bitfile or fpga configuration file or change the RIO#. If you simply edit the content of the FPGA configuration file you should just need to go to the FPGA node and click refresh at the top.

Newer versions of the engine sim add-on allow you to change the RIO#... but pathing changes will still cause issues.

[ToddK]

The FPGA config files are in the same, "..\NI VeriStand 2010\FPGA\" directory but the names have changed to reflect new functionality.  Still use RIO0 as the device address.

Example: Original file "Engine Sim V1_2.fpgaconfig", New file "Engine Sim V1_3.fpgaconfig".

Workspace controls added to show the Crank Angle and Cycle Angle values with the Engine Speed set to 500 return values (0-720).  Changing the fpgaconfig file and redeploying causes the 2 angle values to stay at zero.

[StephenB]

Yeah changing the names will cause the issue.

Can you use the method I described above to see the FPGA front panel values?

[StephenB]

Todd, any updates?