Veristand FPGA Configuration Editor (VCE) - Feedback

[Chuck_81]

Welcome to the Veristand FPGA Configuration Editor (VCE) - Feedback forum. Please use this forum to provide feedback or ask questions.

[ashm01]

Hi,

I created an FPGA project using the FPGA veristand template tool and opened up the newly generated FPGAconfig file in the editor. It threw an runtime error and upon clicking OK , it would terminate the application.

[ashm01]

Any feedback?? I am getting the same problem on multiple machines and various files.

What good is the utility if I cannot edit existing FPGA config Files.

[Chuck_81]

Hi ashm01, sorry for the late reply. Can you post the fpgaconfig file you're using?

Also, have you tried with the latest version of the tool?

Sorry again for waiting,

Regarda

Fabio

[Chuck_81]

Hi, I've found out that version 1.0.1 cannot handle .fpgaconfig file created using the wizard that use PXI RT controller as RT Target.

I've just uploaded version 1.0.3 that should fix this issues.

Let me know if it works,

Regards

Fabio

[ashm01]

Fabio,

I downloaded the latest version and the files which were created using the wizard do load. This surely helps in editing the config files .

Another suggestion(s) for improvement is:

• Ability to drag and drop for packet reshuffling.
• When we add an element , the new element is always on top. Usually we would like to have it at the bottom.

Ash

[Chuck_81]

Thanks for the suggestions Ash, I'll include them in the feature list.

About drag&drop, you currently can select a packet and move it up or down through the packet list by pressing CTRL + UP or DOWN key. It's not a common dran&drop feature but it somehow allows to do packet reshuffling.

Thanks

Fabio

[ElectricWraith]

I've posted part of the problem I'm having to the Engine Simulation Toolkit Feedback thread, but I realize that this is likely a better place for it.

I'm having a couple of problems, one more serious than the other. The first, less problematic issue is with an FPGA config file not opening in the VCE, it throws the same error shown in the first post in this thread. I'm not sure how this particular file was created, I inherited it.

The second, and far more serious, problem is a config file that was created in VCE but throws an error when I try to add the FPGA target to my VS project. I don't have the screenshot handy, but the error text is essentially saying that 'packet 11 in Output' has more than 64 bits. None of the packets in the file have more than 64 bits, and if I delete packet 11, it will give me the same error but tell me it's now packet 10.

Any ideas? What's really odd is that the config file that I can't open in VCE works just fine when I point VS at it to add the FPGA target. Both config files contain the same bitfile name, a file that was created very recently after making some updates and re-compiling the FPGA VI.

[Chuck_81]

Hi ElectricWraith,

can u post the .fpgaconfig file? I'll take a look into it to check what's wrong.

thanks

[ElectricWraith]

Chuck,

I'll have to see if I can attach the working and non-working files to you in a PM as I don't want their contents to be public.

edit: Can't attach files to a PM, so I've attached them here in a password-protected RAR file. I'll PM you the password.

edit 2: Attached both FPGA config files and both bitfiles.