LabVIEW RIO Eval Kit Starter Project (sbRIO-9636)

[Deborah_B]

This LabVIEW 2015 project comes with a precompiled bitfile exposing all of the LabVIEW RIO Eval Kit daughtercard I/O on the FPGA VI front panel and all of the project I/O resources named properly. This project can be used to get started building your own design and allows you to test out all your I/O.

1) Change the IP Address of the LabVIEW RIO Eval Kit in the project (default is 0.0.0.0)

2) Run the FPGA IO Pass Through.vi

3) Modify the FPGA VI to add logic, signal processing, filtering, etc. to accomodate your signals and application requirements

4) Simulate the logic on Windows using the Desktop Execution Node

5) Recompile if you made any changes

6) Expose the necessary I/O on your LabVIEW Real-Time VI by opening a reference to the FPGA bitfile using the Open FPGA VI Reference VI and write to the available FPGA controls or read from the indicators.

For reference, this compilation used the default 40MHz clock and consumed the following resources:

Total Slices: 27.6% (1880 out of 6822)

Slice Registers: 9.1% (4964 out of 54576)

Slice LUTs: 17.1% (4659 out of 27288)

Block RAMs: 0.0% (0 out of 116)

DSP48s: 6.9% (4 out of 58)

For ease of use, every I/O channel has a corresponding front panel control/indicator. To reduce the resources used in your design, only expose the controls/indicators required to do Read/Write  communication with your LabVIEW RT VI.

This is built for the older sbRIO-9636-based LabVIEW RIO Evaluation Kit, the new (December 2015 and later) sbRIO-9637 based kit project is posted here.