IP Node FIR in Virtex 5 SCTL Outputs all zeros (FIR Compiler V5.0 used)

[Denn_Mann]

Hi LabVIEW community,

I am trying to implement an FIR filter in my FPGA to output the cross correlation result of a signal which has 13,000 samples and a reference signal (REF) which has 1,300 samples.  The REF samples are used as the coefficients of the FIR filter which are copied into the FIR Compiler V5.0 using the logiCORE ISE Design Suite from Xilinx.  When I copy these REF coefficients into the GUI of the compiler, I copy them as DBL format and let the GUI take care of the quantization (the preview of the Freq. Resp. looks just fine).  After this, I can generate the IP successfully and paste this into an IP NODE in my FPGA project.  Once in the IP NODE, the IP is generated successfully as well.

Fig 1. Screenshot of logiCORE filter Coefficients

So all I just mentioned seems to be working just fine.  My problem is that, after I compile the FPGA code to run it, I receive all zeros as the output. The way I am running this code is by sending 13,000 samples all at once in FXP format to the FPGA through the "hstTOfpga" FIFO .  Once this FIFO has ALL values in it, the host program ACKs the IRQ0 which can be seen on the screenshot below which is the code contained in the FPGA vi.  After this acknowledgement takes place, the FPGA begins computing the cross correlation coefficients.

In the FPGA code shown below, I have connected the rfd (ready for data) line from the IP Node to the input of the case structure to read a value out of the FIFO only when the IP NODE is ready to accept it.  If rfd = FALSE, the case structure outputs a zero.  Similarly, when rdy (output on dout terminal is valid) is TRUE, a value is inserted into the "fpgaTOhost" FIFO which delivers this to the Host.  The host reads this FIFO only after 13,000 values are placed inside (theoretically, the output of a cross correlation filter should be 13,000 + 1,300 -1 = 14299).

Fig 2. FPGA Block Diagram

The problem is that when I run this code the output I receive are all zeroes.  I have included a graph below which shows some good pointers as to what is going well:

• Non-zero data is going into the FIFO as shown by the "Simulated Wave into FPGA (13,000 values)" waveform which is taken right before values are put into the "hstTOfpga" FIFO
• the "FPGA Notifications" section shown in pink shows that the "n value computed" indicator reaches a value of 13,000 which implies that 13,000 values have been placed into the "fpgaTOhost" FIFO as this indicator is only incremented when the case structure has a TRUE case
• Even though the "Out of FIFO" indicator in the FPGA Notifications section shows all zeroes, I created a latch which searched to see if this indicator is ever non-zero.  This LED is turned on showing that at least 1 non-zero values was read of of this "Out of FIFO" indicator which is what goes into the IP Node in the FPGA code shown above (shown as "Out of FIFO" in Figure 2 above)

Fig 3. Host Front Panel After Simulation

 I really cannot understand what is going wrong with this code.  My suspicion are the following:

• I used the FIR Compiler v5.0 incorrectly and I need to go back and select either a different architecture or paste my coefficients in reverse order to have the cross correlation output correctly.
• I am not placing the IP Node within its own WHILE loop to allow it to complete its processing before the "rdy" line is read. In order to fix this, I would have to replace the current timed loop with a standard WHILE loop and insert a timed loop around the IP NODE.
• My FXP conversions are incorrect and all my data is saturating either in the positive or negative direction.

This is actually a pretty big problem and I have tried to explain the most important points of my particular case here. However, if you would like to get more insight, feel free to download the .zip file attached where I have included the project and the FIR compiler set up I used.

Thank you very much.

Equipment:

Chassis: PXI-1031 DC

Controller: PXI-8102

AWG: PXI-5422

FPGA: 7954r

Digitizer: NI 5761

[JLewis]

It looks like you're missing some handshaking signals on the IP. It needs to have some concept of whether the input data is valid or not--as it stands you're filtering the din value on every clock cycle, regardless of whether the input is zero or a valid sample.

Check your IP pins again, you should find either a data valid or a clock enable pin that can be used to discard invalid input samples.

[Denn_Mann]

Hi JLewis,

I went back to my code and added a "clk" input.  However, this time I was not getting anything returned at all.  I've looked into an article written by the DSP guys at ni.com which is titled "Integrate External IP in the LabVIEW FPGA Module using IP Integration Node"  (http://zone.ni.com/devzone/cda/tut/p/id/10015) and I've been able to get a better picture as to how the handshaking really takes place.

I worked through the example shown and was able to get a returned sinusoid which seemed to be filtered. I've e-mailed the author ([Edit: email removed as it is no longer used for support]) to see if he can provide more details as to his design and implementation.

We'll see what happens but I'll keep you posted.  Its looking to me that a 13,000 coefficient FIR filter is not doable in either MAC or Distributed Arithmetic (D.A.) architectures.  For MAC, I don't have enough DSP48e and for D.A. I doubt I have enough fabric.

I'm thinking this will have to be completely implemented in the computers and the data will have to be post-processed offline.

Thanks for you help.

-Daniel