I have a PXI system with a PXIe-1088 chassis and a PXIe-8822 controller. The system modules include a PXIe-4303 analog input card and a PXIe-7846R FPGA.
The system is being used to control a motor test stand. The PXIe-8822 is sampling a lot of analog instruments via the PXIe-4303 and running an open-loop volts per hertz control algorithm for the motors. The analog sampling and motor controls are running in separate, independent timed loops. The sinusoidal duty cycles calculated on the PXIe-8822 controller are sent to the PXIe-7846R FPGA which does a standard sine-triangle PWM to control the timing of the IGBT gate signals in the motor drive.
I have noticed that when I push the analog sample rate higher (up to the 50 kS/s limit of the card) the motors start to run rough. The motor torques and speeds start to jump around and an oscilloscope shows that the motor currents become distorted and are no longer sinusoidal. The only way this could happen is if the duty cycle for the switches deviates from the nominal sine wave.
I would expect the PXIe-7846R to be pretty robust, given it is an FPGA. My suspicion is that there is an internal data bus limit within the PXIe-1088 chassis that when I increase the analog sample rate it causes a latency in the duty cycles reaching the FPGA. However, none of the timed loops indicate that they are ending late and the CPU loading is staying in the 20-40% range for all four cores.
I am including my real-time and FPGA codes, although this is rather large code with a lot going on so it may not be helpful to someone not familiar with our test system. I'm also including some oscilloscope plots showing good and distorted current waveforms.
