Hello, all.
I'm using the 7966/6581 FlexRIO system to perform timing characteristic measurements for the I2S protocol.
I was wondering whether there is a way to control the strobing point within a particular period of a signal for measurements with respect to another signal.
What I mean to say is, I'm sending a bit clock and serial data from the FPGA that is clocked on this bit clock. Is there a way for me to read back this data with respect to this particular clock and a certain controllable offset? If yes, what is the resolution that this operation can be performed to?
Currently, I'm using an SCTL that is run at a much higher frequency than the bit clock, and the data is reviewed for a write once every tick. The read-back code hasn't been written yet. However, I ideally need to go to about a GHz for the clock of the SCTL if I am to perform setup/hold time measurements using this method. So, if the above operation cannot be performed, can I run the SCTL at that speed, considering that the FPGA module datasheet mentions the maximum I/O data rate to be 400 Mbps (single-ended), or does violating this not come into the question if I'm not going to be writing (or reading) values at that rate?
Moreover, is 400 Mbps the double data rate, or does this assume that data is being clocked only on one edge?
Thank you very much!
