Power Electronics Development Center
cRIO program for controlling 9-level MMC
Hi. Sorry for the slow reply. Things are hectic!
For the interleaved PWM generation with variable phase shift, the most common approach is to use the Discrete Delay IP core in LabVIEW FPGA to phase shift the triangle waveforms with configurable time delay.
The screenshot above is a modification of the GPIC Reference Design Code (unzip to short path, not desktop due to long file paths in the IP cores built using Xilinx Coregen).
Result:
You can find the Discrete Delay block on the palette under FPGA Math & Analysis>High Throughput Math>Basic Elements.
If your triangle generator and the Discrete Delay block is inside a Timed Loop running at 40 MHz, then a delay value of 1 would result in a phase shift of 25 nanoseconds. Since the maximum delay using the Discrete Delay block is 511, the maximum phase shift you can achieve using a single Discrete Delay block is 12.775 microseconds. For additional delay, you could connect a second Discrete Delay block in series, or simply run the triangle generation with Discrete delay in a separate loop running at a lower loop rate. For example, if your triangle generator with delays is running at 2 MHz, then a discrete delay value of 1 would result in a phase shift of 0.5 microseconds and the maximum delay per block would be 255.5 microseconds.
Note that if you don't need run-time variable delay, it's more efficient (in terms of FPGA resources) to hard code the delay in the configuration of the Discrete Delay node.
You may also be interested in reviewing the following presentations and papers on modular multilevel inverters based on LabVIEW FPGA and NI LabVIEW RIO hardware targets:
Dr. J. Curtiss Fox, Duke Energy eGRID Center, Introduction to the 15 MVA Grid Simulator: Challenges in Fault Ride Through Testing
Thomas Keister, TECO Westinghouse Motor Company, Power Electronics Building Blocks: Clemson Power Amplifier Units
Samuel, P.; Chandrashekhar, N.; Gupta, R., "Wind energy conversion based on seven-level cascaded H-bridge inverter using LabVIEW FPGA," Power, Control and Embedded Systems (ICPCES), 2010 International Conference on , vol., no., pp.1,6, Nov. 29 2010-Dec. 1 2010 doi: 10.1109/ICPCES.2010.5698653
Gautam, S.; Kundu, S.; Basu, P.; Gupta, R., "FPGA implementation of generalized modulation for hybrid multilevel inverter with fixed ratio DC lin...," Power Electronics, Drives and Energy Systems (PEDES), 2012 IEEE International Conference on , vol., no., pp.1,5, 16-19 Dec. 2012 doi: 10.1109/PEDES.2012.6484283
Gautam, S.; Yadav, A.K.; Gupta, R., "AC/DC/AC converter based on parallel AC/DC and cascaded multilevel DC/AC converter," Engineering and Systems (SCES), 2012 Students Conference on , vol., no., pp.1,6, 16-18 March 2012 doi: 10.1109/SCES.2012.6199078
You might want to ask the IEEE paper authors above if they would be interested in sharing their LabVIEW FPGA code on this developer community.
Here is a screenshot of the code you sent.
Recommendations:
1. Move the NI-9263 analog outputs to a separate while loop and pass the data to the separate loop using local variables or an FPGA register.
2. For the NI 9263 analog outputs use a single I/O node rather than two separate I/O nodes. This achieves simultaneous analog output updates and prevent arbitration over a single shared resource (the analog output node). In general, always use a single I/O node per module to prevent timing issues and resource contention issues, and only put I/O nodes that can execute at the same rate in the same while loop. The NI 9401 I/O nodes can execute at 40 MHz, whereas the analog output module can execute at 100 kHz, so you don't want them in the same loop.
3. For the NI 9401 digital outputs, use a single I/O node to avoid making separate calls into the same shared resource.
4. For scaling the signals down to the +/- 10 V range of the analog output module, use a multiply function rather than a divide function, and do the multiply operation in the separate while loop containing the I/O node for the analog outputs. A multiply operation can achieve the same effect (i.e. multiply by 1/3276.75 = 0.000305180437933928), but is much faster and uses fewer FPGA resources.
5. Note that the Iterations terminal in the while loop will eventually saturate and stop counting when it reaches its maximum value (2^32/2-1). If you need a loop iteration counter that runs forever, right-click on the loop boundary to add a shift register and increment that inside the loop.
6. Consider what data types you want to use. In this implementation you are using a mix of fixed point, integer and floating point data types in a somewhat confusing way. For example, you convert floating point to I32 before sending to the "sin-tri" chart.
7. If you are intending to scale the control sinewave amplitude in order to control the modulation index, use a version of the triangle generator that does not include the embedded modulation index to reduce resources. Please see attached versions in both fixed point and floating point.
8. The PWM carrier frequency produced by the triangle generator depends on the loop rate interval, dT [seconds]. The Carrier Frequency coefficient to use is equal to your intended carrier frequency fc(Hz) in units of Hz multiplied by 4*dT, where dT is the loop rate in seconds. Therefore, it's important to include code to measure the actual loop rate you are achieving. Here is how to do that by using the Tick Count (Ticks) output of the loop timer. Note that one tick is 25 nanoseconds if you are using the default 40 MHz base clock.
9. For maximum PWM resolution, perform the pulse width modulation inside a single-cycle timed loop (SCTL) executing at 40 MHz. This means moving any operations that cannot execute in a single clock tick outside of the loop. See the GPIC Reference Design Code (unzip to short path) for examples of sine-triangle PWM performed inside a Single-Cycle Timed Loop executing at 40 MHz.
10. The charts you are including inside the loop will only behave correctly when the FPGA is in simulation mode. Consider putting the bundle and chart functions inside a Conditional Compile structure that's configured to only execute in simulation mode (FPGA_EMULATION==TRUE). Alternately, if you use a Desktop Execution Node to test the FPGA code, the chart functions can be included in your testbench application rather than the FPGA application. See the NI Power Electronics Design V Training Course material for details.
11. The Set Line Direction operation only needs to be done once, so move it outside the PWM while loop. Put it in a sequence structure and wire something from the sequence structure to the boundary of the while loop to ensure it executes first. Or, you can set the line direction in the project configuration. Right-click on Mod 8 in the LabVIEW Project tree under the FPGA section and go to Properties.
Thanks for posting your draft code and questions. I'm sure there are other folks in this power electronics developer community with similar questions about how to program in LabVIEW FPGA to achieve the desired timing performance. Don't be shy to reply with follow up question or comments.
