Hi All,
I am using compact rio 9072 for my application in which i am facing following error while compiling my fpga code:
Compilation failed due to a Xilinx error.
Details:
ERROR:TclTasksC:process_077: Failed to complete. Please inspect the log and report files.false
while executing
"process run "Map""
(file "C:\NIFPGA\jobs\XI64xG6_My449tj\map.tcl" line 6)
ERROR:Pack:2310 - Too many comps of type "SLICEL" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.
Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device.
NOTE: An NCD file will still be generated to allow you to examine the mapped
design. This file is intended for evaluation use only, and will not process
successfully through PAR.
This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).
Design Summary:
Number of errors: 2
Number of warnings: 69
Logic Utilization:
Number of Slice Flip Flops: 7,886 out of 15,360 51%
Number of 4 input LUTs: 16,104 out of 15,360 104% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 8,744 out of 7,680 113% (OVERMAPPED)
Number of Slices containing only related logic: 8,744 out of 8,744 100%
Number of Slices containing unrelated logic: 0 out of 8,744 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 17,400 out of 15,360 113% (OVERMAPPED)
Number used as logic: 15,998
Number used as a route-thru: 1,296
Number used as 16x1 RAMs: 82
Number used as Shift registers: 24
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 183 out of 333 54%
IOB Flip Flops: 74
Number of RAMB16s: 1 out of 24 4%
Number of MULT18X18s: 2 out of 24 8%
Number of BUFGMUXs: 4 out of 8 50%
Number of DCMs: 1 out of 4 25%
Average Fanout of Non-Clock Nets: 3.38
Peak Memory Usage: 361 MB
Total REAL time to MAP completion: 1 mins 12 secs
Total CPU time to MAP completion: 1 mins 12 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Process "Map" failed
Start Time: 6:29:23 PM
End Time: 6:44:42 PM
Total Time: 00:15:19
Can Somebody tell me why this error came?
Thanks & Regards,
Vipin Ahuja
