How to stop fpga loop from host VI stop button

[@mjm]

I am running a loop in FPGA (Chassis- Crio 9073) to do measuremt from a sensor. I want to stop the execution of this loop in a safe manner using a stop button on the user interface VI from the windows host machine. Please suggest any existing examples in Labview.

[crossrulz]

It really depends on your architecture.  The simplest way would be to add a Stop button to the front panel of the FPGA and write to it using the FPGA interface on the host.

[@mjm]

could you please explain how to access the stop button of FPGA front panel from the Host FPGA  interface

[Dragis]

Look at http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahost/fpga_interface_palette/, specifically the part on the Read/Write Controls.

[Tirmizi]

Hi,

have your problem get solved ? if not then attach the images of your fpga vi code.

do you read the mesurement data on RT via fpga i.e reading sensor in fpga and then transfer the data via FIFO into RT. Now when you run your code in RT your fpga vi should be run and when you stop your RT code your fpga will also stop.

i you require i will send you a sample RT - FPGA read and display vi.