LabVIEW FPGA compiling error 61330

[hayuan]

Hello,

I am developing a real time MIMO transceiver by using FlexRIO hardware and LabVIEW FPGA with CLIP. When it is compiling a new FPGA VI, it show such an error as below.

Is there anyone who can give some hint on this error? I have searched NI website, but  can't find any relevant discussion on this issue.

I need this issue be solves as soon as possible. Thanks.

  Primary Software:   LabVIEW Modules>>LabVIEW FPGA Module

  Primary Software Version:   2011

  Primary Software Fixed Version:    N/A

  Hardware:    Modular Instruments>>FlexRIO>>PXIe-7965R

The attached also includes the FPGA VI to be compiled. In this VI, 'i_cst12' is an instantiated CLIP (component-level IP).

Regards,

Jin

[hayuan]

Hello,

This issue should has nothing to do with Component-Level IP (CLIP) as I originally thought. I have tried to rebuild other FPGA VIs, which just use LabVIEW FPGA and passed compilation several days ago, giving the same error.

I wonder what is the problem and the solution.

Thanks.

Jin

[Dave-C]

Hi Jin,

I haven't been able to find anything regarding this error either on our site or the Xilinx forums.  To me though, it sounds like your Xilinx tools may require a repair/reinstall to fix a corruption somewhere, especially since you're seeing this behavior with other VIs.  I'm also curious, which version of the Xilinx Tools are you using?  And has this CompileWorker worked previously on this machine?

Regards,

-Dave C

[hayuan]

Hello,

For the CLIP module, I use Xilinx ISE version13.2. And for all IP cores in the CLIP module, I use Xilinx CoreGen version 12.4.

I have built several LabVIEW FPGA Vis on this machine, with or without CLIP module, by using LabVIEW FPGA 2011 and LabVIEW FPGA 2010SP. All of them passed the compilation and works well.

What I am doing now is create a new project, and add the FPGA VIs into the new project and build them.

For the incorrect FPGA VI, it gives the same error.

For the VIs that passed compilation before, they can still compile correctly. However, for these old VIs, I was using Xilinx COREgen version 10.1 to create IPs used the CLIPs in these VIs. For the VHDL source code and ngc files of IPs, this is the only difference between the old (correct) VIs and the new (incorrect) VI.

Below is a snapshot of creating a CLIP.

Thanks.

Jin

[hayuan]

Hello,

After I encountered this error, I have done several tests, which may give you some hints about how to solve the problem.

Test 1. Try to re-compile other FPGA VIs(either with CLIP or without CLIP) in this LabVIEW project, which have passed compile before. They give the same error and stop compile after about twenty seconds.

Test 2. Create a new LabVIEW project, and add FPGA VIs to this new project. And then compile FPGA VIs. If compile the FPGA VI, which have passed compile previously, they can pass compile again. If compile the incorrect FPGA VI, it reports the same error. And after this error, recompile the FPGA VI passed compile just now, it also reports the same error.

Test 3. In the FPGA VI that passed compile, I use Xilinx coregen version 11.5 to generate IPcores of the CLIP. But in the incorrect FPGA VI, I use Xilinx coregen version 12.4 to generate IPcores of the CLIP.

So, use Xilinx coregen version 11.5 to regenerate IPcores of the CLIP for the incorrect FPGA VI. However, when I compile it, it reports the same error.

Some conclusions.

1. Once the error happens, it impacts all the compile afterwards.

2. The version of Xilinx coregen is 11.5 or 12.4 are not the reason.

*************************************

Version Info:

LabVIEW FPGA compile worker 2011

LabVIEW FPGA module 2011

CLIP: Xilinx ISE 13.2, coregen version 12.4. The CLIP has passed synthesis in Xilinx ISE, but I don't do mapping and routing in Xilinx ISE.

***************************************

Thanks.

Jin

[Ben_S]

Hello!

I see that you've posted this same question on techyv.com, however, the time between this thread on NI.com and your new post is nearly 6 months.

Are you still having issues with compiling your code? Are you still getting error 61330? 

Would it be possible to attach a simple project that illustrates the compilation issue?