Hi,
I've developed a custom FLEX RIO module (Digitizer18, 0xAB66 - vendor id) and trying to use it with PXIe-7975R FPGA card (Kintex-7 FPGA)
I have a problem trying to output LVDS signal via aUserGpio(61) and aUserGpio_n(61).
These pins are not K7 clock capable, but I used this FLEX RIO module with PXIe-7962R (Virtex-5 FPGA) where these pins are REGIONAL clock capable and it worked fine.
With Kintex-7 it compiles without errors but i didn't see signals on pins aUserGpio(61) and aUserGpio_n(61), although ADC2_FSM is switching its state.
Is it possible to use pins which is not clock capable to output LVDS or I am doomed to use MRCC or SRCC pins?
Thank you
My xdc file ( aUserGpio(61) and aUserGpio_n(61) belong to Bank 18) :
set_property IOSTANDARD LVDS_25 [get_ports {aUserGpio[61]}]
set_property DIFF_TERM FALSE [get_ports {aUserGpio[61]}]
set_property IOSTANDARD LVDS_25 [get_ports {aUserGpio_n[61]}]
set_property DIFF_TERM FALSE [get_ports {aUserGpio_n[61]}]
# all unused pins of Bank 18 are LVCMOS25
set_property IOSTANDARD LVCMOS25 [get_ports {aUserGpio[49]}]
set_property SLEW SLOW [get_ports {aUserGpio[49]}]
set_property DRIVE 8 [get_ports {aUserGpio[49]}]
set_property IOB FALSE [get_ports {aUserGpio[49]}]
...
part of my vhd clip file (cause it's too large and all other LVTTL logic works fine except LVDS):
attribute dont_touch : string;
signal ADC2_CNV_buf : std_logic := '1' ;
attribute dont_touch of ADC2_CNV_buf : signal is "true";
OBUFDS_ADC2_CNV : OBUFDS
port map (
O => aUserGpio(61), -- Diff_p output (connect directly to top-level port)
OB => aUserGpio_n(61), -- Diff_n output (connect directly to top-level port)
I => ADC2_CNV_buf -- Buffer input
);
....
process ( LVDS_CLK ) -- 200 MHz
begin
if LVDS_CLK'event and LVDS_CLK='1' then
case ADC2_FSM is
when s0 =>
if ADC2_CNV = '0' then
ADC2_timer1 <= (others=>'0');
ADC2_timer2 <= (others=>'0');
ADC2_CLK <= '1';
ADC2_READY <= '0';
ADC2_CNV_buf <= '1' ;
ADC2_FSM <= s1;
end if;
when s1 =>
if ADC2_CNV = '1' then
ADC2_CNV_buf <= '0' ;
ADC2_RESET <= '1';
ADC2_FSM <= s2;
end if;
when s2 => ADC2_FSM <= s3;
when s3 => ADC2_FSM <= s4;
when s4 => ADC2_FSM <= s5;
when s5 =>
ADC2_CNV_buf <= '1' ;
ADC2_RESET <= '0';
ADC2_FSM <= s6;
when s6 =>
if ADC2_timer1 < x"28" then -- x"28"
ADC2_timer1 <= ADC2_timer1 + 1;
else
ADC2_FSM <= s7;
end if;
when s7 =>
ADC2_CLK <= not ADC2_CLK;
if ADC2_timer2 < x"24" then
ADC2_timer2 <= ADC2_timer2 + 1;
else
ADC2_READY <= '1';
ADC2_FSM <= s0;
end if;
when others => ADC2_FSM <= s0;
end case;
end if;
end process;
-- the host uses the rising edge of DCO± to capture D±
process ( UserGClk2, ADC1_RESET ) -- DCO2 echo clock
begin
if ADC1_RESET = '1' then
ADC2_READ_FSM <= s0;
ADC2_BUF <= (others=>'0');
elsif UserGClk2'event and UserGClk2='0' then -- the host uses the rising edge of DCO± to capture D±
case ADC2_READ_FSM is
when s0 => ADC2_BUF(17) <= not D2 ; ADC2_READ_FSM <= s1;
when s1 => ADC2_BUF(16) <= not D2 ; ADC2_READ_FSM <= s2;
when s2 => ADC2_BUF(15) <= not D2 ; ADC2_READ_FSM <= s3;
when s3 => ADC2_BUF(14) <= not D2 ; ADC2_READ_FSM <= s4;
when s4 => ADC2_BUF(13) <= not D2 ; ADC2_READ_FSM <= s5;
when s5 => ADC2_BUF(12) <= not D2 ; ADC2_READ_FSM <= s6;
when s6 => ADC2_BUF(11) <= not D2 ; ADC2_READ_FSM <= s7;
when s7 => ADC2_BUF(10) <= not D2 ; ADC2_READ_FSM <= s8;
when s8 => ADC2_BUF(9) <= not D2 ; ADC2_READ_FSM <= s9;
when s9 => ADC2_BUF(8) <= not D2 ; ADC2_READ_FSM <= s10;
when s10 => ADC2_BUF(7) <= not D2 ; ADC2_READ_FSM <= s11;
when s11 => ADC2_BUF(6) <= not D2 ; ADC2_READ_FSM <= s12;
when s12 => ADC2_BUF(5) <= not D2 ; ADC2_READ_FSM <= s13;
when s13 => ADC2_BUF(4) <= not D2 ; ADC2_READ_FSM <= s14;
when s14 => ADC2_BUF(3) <= not D2 ; ADC2_READ_FSM <= s15;
when s15 => ADC2_BUF(2) <= not D2 ; ADC2_READ_FSM <= s16;
when s16 => ADC2_BUF(1) <= not D2 ; ADC2_READ_FSM <= s17;
when s17 => ADC2_BUF(0) <= not D2 ; ADC2_READ_FSM <= s18;
when s18 => ADC2_READ_FSM <= s18;
when others => ADC2_READ_FSM <= s0;
end case;
end if;
end process;
ADC2_DATA <= "00000000000000" & ADC2_BUF ;
