sbRIO 9627 timing resolution

[brad64]

I am modifying a very mature product that used the USB-6351 DAQ.  This product has years of field data that used the ADC on the DAQ to sample at 300300.3Hz.  This sampling rate is possible because the DAQ uses a 100MHz clock and therefore has a timing resolution of 10ns.  (100MHz/300.300KHz=333 clock cycles).

I am now trying to do an embedded system of this product using the sbRIO-9627 and NI-9222E (ADC) but it looks like I can't get to the 300.3003KHz sample rate because of the on-board sbRIO FPGA clock.  For the sbRIO-9627 the FPGA clock is 40MHz and I've seen that the sbRIO-9629 FPGA clock is 80MHz.  Looking at the following table, these sbRIO clocks do not get me to a time resolution to get the 300.3003KHz sampling rate.

So, to get to the 300.3003KHz sampling rate I have to have a timing resolution of 10ns (100MHz) and the best I can get to with the sbRIO-9629 is 12.5ns (80MHz).  I guess I'm looking for verification of this or obviously a solution (besides changing sampling rate) to get to the 300.3003KHz using the sbRIO.

Note: This system has to be an embedded system that communicates over TCP to a non-ni host computer.

Thanks.  -Brad

[santo_13]

So, you're trying to match the 300300.3Hz rate for consistency with past data?

[brad64]

That is correct.

[ZYOng · Accepted solution]

In LabVIEW FPGA, everything uses 40MHz clock unless they are in a Single Cycle Timed Loop (SCTL). I think the easiest way would be acquiring at the maximum sampling rate of 500kS/s and send the data to RT via DMA FIFO. Then do a software Resample Waveforms (continuous) VI on the RT target using a dt of 1/300300.3 = 3.33E-6

It is possible to do the resampling on the FPGA but it would be more tedious. 

1. Acquire at the maximum sampling rate of 500kS/s and write to an indicator or user-defined register. Use FPGA to resample the data point. 
2. In an SCTL running on the derived clock of 100MHz, read from the local variable or register of the AI and write data to a user-defined FIFO.
3. In another while loop, read from the user-defined FIFO and write the resampled data to the DMA FIFO.

[brad64]

Great.  Thanks for the info.

-Brad