reducing noise in the Vref's for 14 bit pipeline ADC

[deepadc]

I am working with a 14 bit pipeline ADC at 10 MHz clock. The fullscale Input is 4 Vp-p differential. 

There seems to be lot of noise in the VRef's( about 50mV swing noise) and the voltages are given directly from power supply to ADC.

What are the ways to reduce this noise?

[Henrik_Volkers · Accepted solution]

Maybe not the right board. This is pure analog circuitry 😉

.... but what do you expect as an answer if you don't give detailed information about references used, ADC used , schematic and layout?? 

However, look for application notes from linear technology www.linear.com  (look for the ones from Jim Williams!!)   and texas instr. ti.com

Find an anlog circuitry board and post your question, some scope screenshots, schematic and layout there ...

[deepadc]

Thanks