RE: Need help on modifying USRP labview communications 2.0 sample project

[VDN1]

Can someone guide me on how to properly change the "USRP resources.grsc" and "streaming Xcvr (FPGA).gvi". I tried to google but I found nothing. I am using Labview communications system design suite 2.0. 

So here's my question, I changed the FIFO rx stream and tx streams and increased it to 4095. And also created derived clock of 120Mhz. My question is what do I need to change in the "Streaming Xcvr (FPGA).gvi" so that the changes I made (img11.png) will be implemented correctly. Should I set all the clocks encircled in blue in the image img22.png to the 120Mhz derived clock I created?

The sample project I'm using is "USRP RIO 120-160 MHz BW Single-Device Streaming".. 

[hyomeong]

If you only change the size of the FIFO, you do not need to do anything in the FPGA vi (streaming Xcvr).

The derived clock is used in a loop for your own algorithm, not for the existing loops. Do not change the clock.

[VDN1]

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@hyomeong wrote:

If you only change the size of the FIFO, you do not need to do anything in the FPGA vi (streaming Xcvr).

The derived clock is used in a loop for your own algorithm, not for the existing loops. Do not change the clock.

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Thank you for replying. I thought it matters since I saw a "fifo 0" (encircled in attached img33.png). Thank you for clarifying this up. 

I was thinking that by increasing the clock speed using derived clock in the loops of "Streaming Xcvr (FPGA).gvi", throughput will be improved as what I understood in this article http://www.ni.com/en-ph/innovations/white-papers/13/make-it-faster--more-throughput-or-less-latency-.... 

[VDN1]

I forgot to upload the img33.png so I attached it here. 

[Stop_Luke_and_Listen]

Hi VDN1,

The Data Clock in the transceiver loop is going to determine the max rate at which IQ samples are acquired.  This rate is then decimated to acquire at the requested IQ rate.