Reducing USRP decimation BW

[cochenob]

I have an application that would benefit from a BW/sample rate lower than the ~200kHz minimum that the current driver seems to provide.

Is there any way to configure a lower BW?  What currently limits the decimation rate/filter BW?

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Brandon

[Tim-C]

Are you getting an error when you set an I/Q rate lower that 200K? If the driver is set to not allow less than 200k then you are just limited to that, but that shouldn't matter because you can always run your data through a loop and delete samples to make it a slower rate.

What device are you using?

[ErikL]

The modulation toolkit includes a fractional resampler for complex IQ signals. The POCSAG pager demo uses this on the USRP community. Another solution as Tim mentions is low pass filtering to prevent aliasing and then removing samples. This only works if the old rate and new rate are multiples. You would need to do the second method for both I and Q.

[cochenob]

No errors.  Just seems like for input sample rates below 200kHz...the coerced sample rate seems to stay at 200kHz...suggesting that there's some limit with regard to the decimate-by-N procedure. 

And yes...I've been looking at doing my own filtering/averaging in LV to get lower BW's.  I was just hoping that I could configure the hardware to do it for me, as my application is time critical (i.e. - I want to try and do as little between fetch's as possible).

I forgot about the fraction re-sample VI's in the MT.  I'll take a look at those.  Might take the pain out of writing my own code (though won't resolve the issue just mentioned).

Just for my own understanding...what is limiting factor here in the hardware?  i.e. - what's the limit on N?  200kHz is a factor of N=500 less than the 100MS/s ADC rate...which is close to 2^9...but a 9-bit word for N seems like a strange number.  Just trying to gain some insight here.

Thanks!

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Brandon

[ErikL]

The Decimation from the 100MS/s ADC happens in the FPGA. The chain is:
Divide by 2, divide by 2, divide by N
(N= 1 to 125). So 200k is all decimation at its maximum in the FPGA.

[cochenob]

Got it.  Pulled out the Block Diagram and see the N=1-128, N=2, and N=2 decimation blocks.  If I were able to poke into the FPGA myself, would I be able to have more flexibility here?  (i.e. - could I add more decimation stages)?  I'm guessing this has something to do with FPGA resources?

[mishrashirish]

Hello Brandon,

I am having same problem, can you descibe me how did you solved your problem

[cochenob]

Never had a chance to go back and look at this again...but the solutions that Erik and Tim mention seemed like the way to go.  i.e. - filter and decimate/resample in LabView after fetching.

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Brandon