I have an RxStreamer overrun error code when I try to accomplish the following RFNoC receiving chain using USRP-X440. I want to test one RadioRx channel samples data at master clock rate of 360MHz, statically connect to a DDC to decimate the rate down to something like 10MHz and connect to RX Streamer. In my application, I remote stream data using RxStreamer (via 10GB) to my host IP address and look at the receiving data using Wireshark.
I simply use the default X4_400 image, remove the replay block, adding the ddc block, and simplified to one single channel. I was able to run the the receiving chain with MasterClockRate set to 266.24MSPs and DDC rate set to 10MHz. I also confirmed that the receiving data is at correctly 10MHz.
However, when I change only the sample rate to 360MSPs (keep DDC rate the same as 10MHz), it immediately gives me Overrun Error Code at RxStreamer. This does not make sense to me because RXStreamer expects the same 10MHz from DDC, and increasing the MasterClockRate should only affect the data rate between RadioRx->DDC, then why do I have overrun error code at RxStreamer?
I did some math of data rate of 266.24MSPs*(32-bit per sample) = 8.51GHz, and 360MSPs*(32-bit per sample) = 11.52GHz (above 10GBs)? But again, this data rate should only be routed to the DDC, then how does it cause overflow in RxStreamer? I cannot find any routing error in my image core file.
I also tried to increase CHDR_W and CHDR Ingress Buffer but still see the same behavior with overflow. Could someone please explain what might go wrong here? I use all the default RFNoC block (Radio, DDC). I use the rfnoc_rx_to_file.cpp but only change the streaming argument to specific ip address of my host to stream to. And the below is my RFNoC yaml configuration
# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
copyright: >- # Copyright information used in file headers
Copyright 2023 Ettus Research, a National Instruments Brand
license: >- # License information used in file headers
SPDX-License-Identifier: LGPL-3.0-or-later
version: '1.0' # File version
chdr_width: 128 # Bit width of the CHDR bus for this image
device: 'x440' # USRP type
image_core_name: 'usrp_x440_fpga_X4_400' # Name to use for the generated output files
default_target: 'X440' # Default make target
inherit:
- 'yaml_include/x440_radio_base.yml'
- 'yaml_include/x4xx_x4_base.yml'
parameters:
RF_BW: 400
ENABLE_DRAM: False
NUM_DRAM_BANKS: 0
NUM_DRAM_CHANS: 0
DRAM_WIDTH: 128
# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
ep0: # Stream endpoint name
ctrl: True # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size_bytes: 262144 # Ingress buffer size for data
# A table of which crossbar routes to include
# -------------------------------------------
# Rows correspond to input ports and columns correspond to output ports.
# Entering a 1 includes and a 0 removes that route from the crossbar.
crossbar_routes:
# eth0 eth2 dma ep1 ep3 ep5 ep7
# eth1 eth3 ep0 ep2 ep4 ep6
- [ 1, 0, 0, 0, 0, 1] # eth0 (QSFP Port 0, Lane 0)
- [ 0, 0, 0, 0, 0, 0] # eth1 (QSFP Port 0, Lane 1)
- [ 0, 0, 0, 0, 0, 0] # eth2 (QSFP Port 0, Lane 2)
- [ 0, 0, 0, 0, 0, 0] # eth3 (QSFP Port 0, Lane 3)
- [ 0, 0, 0, 0, 1, 1] # dma
- [ 1, 0, 0, 0, 1, 0] # ep0 (radio0.0)
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0:
block_desc: 'radio.yml'
parameters:
NUM_PORTS: 1
NIPC: RADIO_NIPC
ddc0:
block_desc: 'ddc.yml'
parameters:
NUM_PORTS: 1
# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect
# - srcport = Port on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Port on the destination block to connect
connections:
# RF A:0 RX
- { srcblk: radio0, srcport: out_0, dstblk: ddc0, dstport: in_0 }
- { srcblk: ddc0, srcport: out_0, dstblk: gain0, dstport: in }
#
# BSP connections are inherited from YAML include files
# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
# - srcblk = Source block to connect (Always "_device"_)
# - srcport = Clock domain on the source block to connect
# - dstblk = Destination block to connect
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: ce, dstblk: ddc0, dstport: ce }
# Other clock domains are inherited from YAML include files
Thank you!
