- Is it possible for the USRP-2940 to continuously process, in real-time, two inputs and transmit two outputs with 1 MHz bandwidth at 80 MHz center frequency using LabView, USB 3.0 and Windows?
This 2940 is appropriate hardware for this. It can tune to that center frequency, can decimate to that required bandwidth in the FPGA and has 2 simultaneous Rx channels (and 2 Tx channels). The connection to a host PC is either 1/10 GbE or PCIe x4, NOT USB 3.0.
What latency can I expect (assume minimal CPU loading, like a simple FIR filter) from analog input to output when running on Windows? Can this be improved if I use LabView and the USRP with a PCIe interface card and real-time patched Linux?
It's hard to say without knowing the processing you want to do, and on how much data. The PCIe interface is more than enough to stream your 1M BW back and forth... so it all depends on how much data you stream, what you do with it on the host, and the capabilities of your processor. But it also sounds like your processing could be easily done on the device using LV-FPGA. There are built-in primitives for FFTs, FIRs, etc.
Once I develop an algorithm in LabView's graphical interface, is it as simple as clicking a button to burn it onto the FPGA for low latency execution? Or do I need to know Verilog/VHDL or a lot of details about FPGA architectures?
You definitely do NOT need to know Verilog/VHDL. You can do it entirely in the LV environment. As for porting Host LV code directly to the FPGA, Yes and No. Most of the LV code you develop for a Host VI could be compiled for an FPGA target (obviously, not stuff that would display a graph or write to files, etc.). You might have to replace some Host processing VIs (like a FFT VI) with a FPGA VI with similar capabilities for best performance. The basic idea would be that you could develop your IP on the Host, then target your VI for the FPGA, but you might have to manually tweak some stuff (add pipelining to meet timing, replace some Host-only VIs with their FPGA equivalent).
What latencies can an FPGA implementation achieve?
The processing loops for the LV-FPGA target can run at 100 MHz or 200 MHz. The latency will depend on your processing, and how much pipelining you need. There are high thoughput FPGA VIs (like, for FFTs)... I don't know the latency off the top of my head, but say it's 500 cycles to get a 256-bin FFT. That would be ~5.1 us in a 100MHz clock domain.
What software packages do I need for just Windows/Linux and also for FPGA development? This is for research, not developing the next iPhone, so budget is tight.
You would need LV/LV-FPGA. The NI-USRP driver and USRP-RIO support is free and comes with some DSP toolkits. I'm not sure of the current pricing of LV-FPGA and the hardware itself.
Hope this helps your decision.
