Digital Filter on Sample Clock 6601/6250

[ugip]

Hi,

I am using a PCI-6601 (Dev1) and PCI-6250 (Dev2) card connected via RTSI cable.

I apply a PWM signal to ctr0 of the 6601 (/Dev1/PFI38) and enable digital filtering (100ns) on the respective task (period measurement).

I apply an analogue signal to AI0 of the 6250 card. As I am interested in an analogue measurement sample when the PWM signal rises from low to high, I have set the sample clock source of the AI task to "/Dev1/PFI38" and the sample clock active edge to "Rising".

Everything works just fine, but I have one question:

Is the sample clock for the AI task the filtered PWM signal or the unfiltered PWM signal?

Regards,

Udo

[John_P1 · Accepted solution]

Hi Udo,

Great question!  The digital filters are actually not part of the counter subsystem, but rather the PFI line itself.  So, if you have enabled the digital filter for a specific PFI line, the signal you route to any subsystem from that PFI line will have already gone through the filter.

This is actually the workaround for enabling PFI filters on M Series / TIO DAQ devices when you are not using counters (the hardware supports filtering on every PFI line but the DAQmx driver only allows filtering as a part of counter tasks on these devices).

I also wanted to point out that the 6250 itself has 2 on-board counters, so you could do the same thing using just the 6250 (unless you are using more than 2 counters).  I hope this helps!

Best Regards,

John

[ugip]

Hi John,

thank you very much. That was the answer I was hoping for.

By the way, I need all together 5 counters for my measurement task, so that's why I need the 6601 in addition to the 6250.

Regards,

Udo