Counter/Timer
counter pause trigger problem
- last edited on by
migration-bot
Hi Christian,
Great question. You can't use a Sample Clock and Pause Trigger on the 6259 at the same time (they both use the same pin on the counter chip). What you would want to do is configure a buffered Pulse Width Measurement (see diagram from M Series User Manual😞
It's not necessarily the most intuitive, but you would need to use the external gate signal as the pulse signal to be measured. You can measure this in terms of ticks of an external "timebase" (in this case, your photon counter). Configuring "Implicit" timing means that the value of every pulse will be latched in to a buffer.
However...
The on-board FIFO is essentially non-existant for counters on PCI M Series DAQ Devices. If you try to clock data in faster than can be pulled from the board sample-by-sample you will receive an error. For PCI M Series, we have benchmarked counter inputs at around 380 kHz maximum (system dependant). The PCIe M Series boards use a bridge to convert PCI to PCIe, if anything performance would be slightly worse on these boards (I don't have a benchmark handy for these).
Also, a 50 ns gate time doesn't give you much time to count photons. How many photons are you expecting to count in this interval? How wide are the TTL signals produced by each photon?
So, I see two problems with this:
- The 6259 can't sample the counter at 1 MHz. This could be remedied by switching to an X Series board (e.g. 6320), which features a counter FIFO and can sample a counter at rates exceeding 10 MHz.
- The 6259 is only specced to accept an external source up to 20 MHz. Having a 50 ns wide gate would only give you either 0 or 1 counts given that your external source is within the spec. X Series is specced to 25 MHz so switching wouldn't give you much help. You might be able to go higher than this if your signal is clean enough but I can't make any promises.
Best Regards,
- last edited on by
migration-bot
Hi Christian,
You can count external signals up to 20 MHz. Also, you could count the 80 MHz timebase (its bandwidth isn't limited by the protection circuitry on the digital front-end). So the M Series counter can certainly count faster signals than 380 kHz. This benchmark represents the maximum rate that you can sample data from the count register.
All X Series boards do allow the use of both a sample clock and pause trigger. The reason is that they have a dedicated pin on their counter chip for a sample clock input (M Series and earlier boards used the Gate input for the sample clock). The gate input is used to implement the pause trigger. See the following image from the X Series User Manual:
The items circled in Red are unique to X Series boards and are not present on M Series. The FIFO allows us to sample X Series counters at a faster rate than other boards (10 MHz or so per counter).
The buffered Pulse Width Measurement approach depends on you sampling the count register at the falling edge of every gate signal. It sounded like your gate signal is 1 MHz, which would be too fast for M Series counters. If you slow the gate signal down to the 380 kHz range then this method should work on your M Series. The setup code would look something like this:
All X Series boards have the same counter features. They allow fast enough sampling to do the buffered pulse width measurement method, as well as provide for the simultaneous use of a pause trigger and sample clock. It might make more sense to get a low cost X Series to do your counter operations (the PCIe 6320 is the introductory X Series, while the PCIe 6353 would be more of a direct replacement for your 6259).
Best Regards,
Hi Josh,
If you configure your device like the following it should work (just tested on a PCIe-6353):
In my case, PFI8 was connected to an encoder that I manually rotated to produce pulses, and PFI0 was connected to a button which would pulse low to reset the gate signal. I was able to report cases of 0 encoder pulses during the gate.
If you're configuring the hardware differently then you might encounter errors. Make sure you have Implicit Timing selected from the polymorphic VI and that you are using the same terminal names that I am for your signals (CI.CtrTimebaseSrc for the photons, and CI.PulseWidth.Term for the gate). If you had an external sample clock configured (instead of using imlpicit timing) then you might get errors if you receive two consecutive clock edges without a pulse width (which is actually the gate), but this probably isn't what you want to be doing anyway.
Best Regards,
