RX AGC implementation in FPGA

[wheberth]

Hi all,

I'm working to implement a closed loop AGC function in FPGA in order to keep signal amplitude at ADC inputs of USRP-RIO inputs at a desired level.

Looking at the schematics is possible to see that the RF attenuator control pins (6 bit parallel)  from the SBX/CBX frontends are connected to directlty to FPGA pins but we can't find information on how to write to those pins directly from clock driven logic.

Can someone tell me if that is possible and where can I get more information on how to do it?

Looking at the code of some examples it is possible to see references to "ATR Register", but I coudn't find a register map or any more detailed information.

Best Regards

Wheberth

[lferreira]

Hi,

USRP driver doesn't give you access to FPGA pin connected to attenuator, to modify attenuator gain to implement an AGC you need to set parameters of gain through the driver that automatically assigns the related register.

The 802.11 Application Framework 2.0 implements an AGC gain control on FPGA.

https://www.ni.com/en/support/documentation/supplemental/15/labview-communications-802-11-applicatio...

You can dig into Set Gain.gcdl to bring up the Register adress for gain.

Regards,