LabVIEW FPGA Idea Exchange

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labviewman

Allow FPGA User Defined Variables to be relative-referenced instead of absolute-referenced

Status: New

When using FPGA code on a different target, you can copy/paste all the User Defined Variables (UDV) to the new target, but you must manually re-link every UDV in the FPGA code to the UDV on the new target, which is a very tedious process when there are more than a handful of UDVs. Having the UDVs relative-referenced would make the FPGA code much more portable. On a cRIO, I always use FIFOs, but UDVs are the only method of getting data out of an EtherCAT chassis.