Incremental Compile LabVIEW FPGA

[e.ono]

Hello all.

It is time-consuming that we have to compile all LabVIEW FPGA code even if there is tiny little change on FPGA code.

I understand there is sampling probe, Desktop execution node and simulation tools to reduce such time.

Our customer in Japan, would like to use incremental compile function also on LabVIEW.(Please see below)

I agree his opinion.

http://www.youtube.com/watch?v=9v50uCVdW3o

What do you think?

Eisuke Ono

Application Engineer at National Instruments Japan.

[Dragis]

I think this is something everyone would like to see, I'm glad someone finally posted an idea for it to get feedback from the community. With the introduction of (better) incremental compilation in the latest 3rd party tools like Xilinx there is certainly some features the LabVIEW FPGA compiler could take advantage of. There is also plenty of optimizations within the LabVIEW FPGA compiler itself that could help. 

The problem with incremental compilation of any kind is doing it well enough that the majority of use cases don't suffer performance issues when squeezing application changes into as few changes in the actual hardware. Getting this balance right takes a lot of work and a lot of sample applications to try it against.

[Mr._Jim]

Just to clarify, my vote for this one comes with serious respect to the manifold technical challenges that will likely be encountered, as alluded to by Dragis.

Nonetheless, I think it would be fantastic if it could be implemented well.

[Intaris]

As long as we can still opt to do a full compilation im in.

[ToeCutter]

The importance of this one is only going to increase as the growth in FPGA complexity continues to outpace the single threaded CPU performance required to synthesize designs.

[Rodéric_L]

I wish it was already implemented.

When changing even a COntrol name, I have to compile again, and it takes nearly 5 hours... It makes it so hard work with it when you need to code and fix when validating the system with  the customer.

Short story, I'm also working on a project and we use VHDL IP, so the VHDL guy asks me: Why would you compile everything? it will take forever... I explain him the issue, and he told me that it should be easy to compile only the modified functions (i.e modifying a sub vi should compile only the shub VI and a small portion of the calling VI)

[deadbug]

Not sure if this a dead idea, but I would very much like to see incremental compile option.  As noted above, even a minor control name change means recompiling everything.  Heck even just changing the size of the front panel means a recompile.  The other thing is the Xilinx IP.  This shouldn't need to get built every time unless something was changed.  If you work directly in Vivado, this is how they operate.  It makes no sense to recompile/synthesize the entire project when nothing has changed, especially the Xilinx IP cores.

[crossrulz]

deadbug, If you like this idea you need to give it a Kudo.  A comment does not count as a vote for the idea.