Make generated VHDL files accessible

[komorbela]

As the compilation goes on of the LabVIEW FPGA code to bitfile, there is an intermediary step when a VHDL file (or maybe Verilog?) is generated. This file would be very beneficial if you want to use another FPGA target, that NI supports. I know that this VHDL file cannot be directly used for non supported FPGA, but it would be a very good starting point for the ones that know VHDL language.

[Intaris]

This would mean opening up NI's know-how in controlling their hardware which (even as a NI customer) I can fairly accurately predict will NOT happen.

[komorbela]

I don't mean exactly the whole VHDL. It could be the part that is directly related to the LabVIEW code, the hardware related special stuff cannot be used reliably for other hardware targets anyways.

But even in this case you are right:

- The NI would loose on RIO sales in the beginning...

- but may win on selling LabVIEW with FPGA module. Currently this combination sells at about $5000.

As time goes on the popularity of LabVIEW for FPGA may cause higher demand even for RIO devices and even could cause RIO prices to drop. (and maybe FPGA module prices)

What a nice world it would be:)

[Dragis]

@Intaris, don't be so gloomy : ) The nice thing about the idea exchange is that you can push for something and perhaps get NI to see the value and add it.

The key thing here is determining how exactly people would use this generated IP if available? For instance, if the answer is simply to have it pre-generated for use in an IPIN or CLIP implementation then the work required would be much less than that required to target a completely independent family of devices.

One thing to note is that you can see the VHDL associated with your design if you use the third-party simulation feature.

[Taylorh140]

It would be nice to program embedded fpga solutions in labview! 

[Jorn_Deruyck]

The generated intermediate VHDL code is "encrypted" with a XOR cypher, which is fairly easy to decypher if you know what you expect to find in such a VHDL file.

Unfortunately, as with any proceduraly generated code, it isn't quite as readable as you would want.

In terms of portability towards other FPGA targets, i assume that basic pure G algorithms would be portable, but beyond that, there wouldn't be alot of use cases since the added value of LabVIEW FPGA is the IP to commuicate with LabVIEW hardware. (modules, Real Time system.. etc)

I guess the reasoning to "encrypt" them is similar to the fact that most VI's in vi.lib are password protected: To hide unreadable code and to prevent users from poking around in stuff that potentially could degrade the functionality of the product. And only to a lesser extent to protect intellectual property. (which is protected by law)