LabVIEW FPGA Idea Exchange
Perhaps there's already a good way to do this, but some structures/nodes are allowed in a Single-Cycle Timed Loop but their behaviour is significantly changed, perhaps breaking your VI.
It would be good to be able to mark VIs in some way as unsuitable for use within a SCTL.
An example is the flat sequence structure - you can place this in a SCTL and it can pass intermediate file generation, but the behaviour is as if there was no sequence structure.
Assuming that it isn't always superfluous, this probably indicates invalid behaviour but is not necessarily obvious to detect (e.g. with broken compilation or intermediate files).
Some specific node that could be placed on a block diagram and indicate that a VI cannot be placed inside a SCTL would be useful.
Something like a Divide can be used for this, but not trivially easily - you need to actually use the output of the Divide or else the dead-code elimination allows the intermediate files to be happily generated. It took me quite a few goes to get a failure even with SGL precision divide in a SCTL... wiring to a structure or an indicator is not enough, it must be something that actually uses the value.
Hello,
Great idea. In NXG, we made SCTL a separate model of computation (called Clock Driven Logic) so that when you have an FPGA VI, you have a separate set of palettes for inside-CDL support and outside-CDL support. This would be a major infrastructure change to LabVIEW FPGA of today, but it is definitely a pain we have heard a lot.
What hardware do you currently use?
Thanks!
Rahul