Simplify the display of Single Cycle Timed Loops in LV FPGA

[gsussman]

Single cycle timed loops are a huge performance enhancer in LV FPGA. We learn to use these very prolifically in and around our code to save precious FPGA space, yet the BD representation of the SCTL is the standard Timed Loop structure, with both the Left and Right "ears" visible as well as the conditional terminal.

I propose that the SCTL be given it's own representation on the block diagram, one without the "ears" and without the conditional terminal (by definition it only runs once). This will promote much cleaner looking FPGA code and more readable diagrams.

[Donovan_B]

The Single-Cycle Timed Loop doesn't necessarily only run once.  What the name means is that all the logic for the code inside the loop can be completed in a single cycle of the clock governing the loop.  In a regular while loop, intermediate registers are placed between function nodes to enforce dataflow.  The Single Cycle loop has no such registers, which saves time and space.  The loop can run many times, and will run infinitely if you do not wire anything to the conditional terminal.  This is very useful for fast sampling of digital control lines!

The "ears" (at least on the input) are useful for specifying which clock governs that loop.  If you have a derived clock of 80 MHz and want the loop to run at that rate, you can wire a control to that input and use the loop in a subVI to run at 80 MHz.

[RavensFan]

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gsussman wrote:

 and without the conditional terminal (by definition it only runs once).

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I don't think this is true.  It runs more than once.  If it didn't, it wouldn't be called a "loop".  All single cycle means is that all the code inside that loop can execute in one clock cycle, not it only executes once.

[Brian_K.]

Perhaps an alternative to this suggestion is a single cycle frame.

[Marc Blumentritt]

I like the idea of the single cycle frame.

[muks]

Bring on the single cycle frame......

[Pcorcs]

I like the idea of differentiating the Single-Cycle Timed Loop from the RT Timed Loop Structure; however, on the FPGA, I believe the Timebase selection should still be accessible for single cycle loops. I'm not sure how that selection would integrate with the frame display.

[Dave_Thomson]

Having a dedicated structure for this on the pallette (even if it is the same to the compiler) would further make novice users more aware of this valuable concept and promote its appropriate use by all users.

[James_McN]

I think you do need the display of the time used. Maybe the node can be redesigned to remove the ears and show this, or at least change the resize function that means LabVIEW doesn't allow nodes under them when it auto expands!

[Manzolli]

I like the idea of the single cycle frame too.