I'm currently writing a debug tool to test communications between FP objects on my host VI to a RT system and then to a FPGA system. I thought I would "simulate" all three layers with Queues in between in order to make sure that the parameters are being received int he correct manner - a complete Communications test so to speak. I want to be able to run this VI on the host. There are a lot of bits being shifted and twisted and being able to set probes and braekpoints within a single host VI is of great advantage.
Initially, it worked fine after copying my FPGA code (with Objects instantiating registers and then reading from and writing to them) but now then LabVIEW did another disappearing trick (with no goodbye or anything). When I say it worked, the Values being read from the FPGA objects which instantiate their own registers were showing the correct values when being sent data. This means that LV really did instantiate the registers and was able to address them all individually.
Since then I'm getting the error listed in the title every time I try to run the VI.
1) Do I really need to move my FPGA parts to a VI on the FPGA target and have the VI running in parallel with the target set to run in Dev mode (and sending data over DMA channel)
2) Why did this work initially and then fail?
Shane
