Export FPGA Onboard clock to io modules

[MaJahn]

Hello,

Is it possible to Export the FPGA Onboard clock, or any derivates, to any I/O Modules?!

Greeting

Matthias

[muks]

looking for this

[MaJahn]

Jear but this is not what I want! ^^

Sorry in my first post i didn't express my self right!

So I want to use the Reference Clock (40MHz)  of my FPGA chip to export to an I/O Modul and use it instead of their own Reference Clock (12,xxx MHz)!

Object iss to measure faster...^^

Thank you 

der Matze

[RyanB]

Which FlexRIO IO Module are you using?  This will help determine which signals you have access to drive via the standard CLIP's.

In general, I use the DDR flip-flops in the FPGA to drive a clock signal on an I/O pin.  This way you have a deterministic timing relationship between the internal and external copies of the clock.  This matters if you are using the clock to transfer data between the FPGA and the IO Module.

You can instantiate a DDR flip flop in the IO Module CLIP or in a user CLIP.

-RB

[MaJahn]

Hello,

Iam using a NI cRIO 9014 with an cRIO 9118 and an cRIO 9104 FPGA Chassis.

MJ

[RyanB]

Ah - my answer applies to FlexRIO adapter modules.  I am not familliar with the options for exporting clocks on the cRIO platform.

-RB

[MaJahn]

Hi,

For no one else has a idea or knowledge which he denies with? 

Have a nice weekend and a Successful WorldCup

Matze

[Donovan_B · Accepted solution]

I am assuming this is referring to an NI 9225, 9227, 9229, or 923x module in a CompactRIO chassis.  You cannot export the onboard 40 MHz clock to these modules.  One of the modules must be a master and then you can synchronize the timebase for all modules by setting the Master Timebase Source in the C Series Module Properties dialog.

Exporting the 40 MHz clock would not allow you to acquire data much faster anyway.  Depending on the frequency of the timebase, you can calculate the data rates using the NI 9225 Operating Instructions and Specifications.  However, you are still limited to sample rates within the specified data range.  For a timebase other than 12.8 MHz, your maximum possible sample rate will only be about 51.2 kS/s instead of the available 50 kS/s with the 12.8 MHz timebase.

[rabiskar]

Hello Donovon,

I have the same issue. I am acutally trying to access the 40 MHz onboard clock usng a FPGA Referance open.VI. But I am unable to access the onboard clock outside the FPGA block. 

I read your comment on synchronizing the clock to 40 MHz but I couldnt understand how can I accomplish the same. 

Thank you in advance. 

Rabi