FPGA Timing Error From Simple Change

[Alex1777]

Dear experts,

Hardware/Software Background:

I am working on an FPGA vi using the 7966R FPGA and 5734 AI. I am using LabView 2012 SP1.

Problem Background:

I have a working project where in my FPGA.vi, I use the boolean output of SubVI-Threshold.vi to as a logical condition to save data. There is another sub vi, SubVI-Ratio.vi where the boolean output is not used for any decision except being placed into an AND with the output of SubVI-Threshold.vi. This version compiles at my requirement of at least 40MHz. A screen shot of this part of FPGA diagram is attached as Does_Compile.png.

Problem:

However, when I use the logical AND between the outputs of SubVI-Threshold.vi and SubVI-Ratio.vi seen in Does_Not_Compile.png, I get the timing error seen in TimingError.png. I believe I am implementing Pipelining correctly with my feedback nodes and do not understand the references given in the Non-Diagram Component. I am still a novice at FPGA (and Labview in general) and would greatly appreciate any de-bugging suggestions.

I have also attached the project (the version which does not compile although the version which does can hopefully be retrieved from the pictures if needed). Please excuse my plethora of Feedback nodes and comments they originate from attempts to debug this problem as well as documenting my work. 

Thanks in advance for any advice, suggestions, or help anyone is able to give!

Cheers,

Alex

[David-A · Accepted solution]

You may find the LabVIEW High-Performance FPGA Developer's Guide useful if you're new to labview fpga. It has some advice on timing closure techniques. 

https://www.ni.com/en/support/documentation/supplemental/13/the-ni-labview-high-performance-fpga-dev...

It looks like you have a large design. Its common for small changes to have a disproportionate impact on the timing performance of a design due congestion issues as you approach the resource limits of an fpga. Here are some suggestions:

1. Use less of the fpga. This sounds obvious, but if you haven't had a reason to be selective with your resources thus far you may find some low hanging fruit when it comes to removing unnecessary parts of the design. Or possibly optimizing some parts that were easy to code using resource intensive methods but now require a second look. Doing so will reduce congestion and improve timing. 
2. A low effort method of meeting timing is to move your processing logic to a slower clock domain and only acquire data in the faster clock domain. The downside is the slower clock domain won't have the same throughput so you may not be able to stream continuously depending on the application. But if you were taking finite records you may find the strategy of moving processing to a slower clock domain effective.
3. Remove the enable chain from the processing loop. This is an advanced timing closure technique, but it is helpful when a congested design can't be reduced in size or moved to a slower clock domain. Note that not all clock sources support gating, which means that you may need to move your data to a clock domain other than IO Module Clock to leverage this option. Here are some links that further explain this.

https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/improving-timing-performance-in-large-...

https://www.ni.com/docs/en-US/bundle/labview-fpga-module/page/dataflow-and-the-enable-chain-in-fpga-...

[Alex1777]

Thanks for the pointers. I went back and optimized older parts of the code which worked and minimized number of calculations and this did the trick. Thank you much!