Hi,
I would appreciate help on this topic
.
I was trying to compile my project code for the SBRIO 9629 (similar code was previously used with CRIO 9056 with NI 9401 modules, or SBRIO 9638).
It was then I realized the 96 digital i/o are not SCTL compatible (error thrown during compile).
The SBRIO 9629 96 RMC digital i/o have a typical sampling rate of 10MHz (compared to the NI 9401 modules 9MHz with 8 lines active)
The NI 9401 and SBRIO 9629 28 digital i/o are SCTL compatible, however based on this compilation error, it seems the SBRIO 9629 RMC digital i/o are not.
I've had no issue with SENT signal decoding or PWM signal generation (which require 5MHz sampling) on either SBRIO 9638 or CRIO 9056 with NI 9401.
In those cases, I use SCTL's for the pulse counting (for SENT signal decoding) or pulse generation (PWM) for motor controls.
So these loops runs at a rate of FPGA clock of 40MHz (with the digital signals updating at 9MHz NI 9401, >10MHz? on the 9638).
Question then is:
How do I ensure my FPGA pulse counting and pulse generation loops run as fast as possible? I.e. at least 5MHz?
I'm thinking to keep the code the same as SCTL code, but use a while loop and run it with a delay of 100ns (10MHz)
I understand this would increase FPGA resources compared to just using a SCTL, but seems I don't have much of a choice as the i/o are sufficiently fast but not SCTL compatible.
At least the 9638 has much larger FPGA (200T vs 75T of the CRIO 9056).
Background on the project:
Valve position control and data acquisition
The fast signals requiring the use of the FPGA are:
SENT digital signals for position feedback
- SENT signal tick (time) base is 3usec, meaning needs at least 0.3usec sampling for robust decoding (~3MHz)
Up to 20KHz PWM signal is generated :
- Need at least 5MHz sampling so that have sufficient resolution for control purposes ( 5 MHz / 20 KHz PWM = 250 increments)
Thank you!
Matt Lawson
